E&L Instruments
An kiterplex Electronics Company 70 Futon Terrace, P.O. Box 1642 New Haven, Connecticut 06512
(Z03) 824-3103 • FAX (203) 468-0060
Published by E&L Instruments®,
An Interplex Electronics Company
70 Fulton Terrace, New Ha von, Connecticut 06512
Copyright © 1990 by Russell L. Hdserman & Preston Barber
All rights reserved. No part of this book shall be reproduced, stored in a retrieval system, or transmitted by any means, electronic, mechanical, photocopying, recording or otherwise, without written permission from the publisher. No patent liability is assumed with respect to the use of the information contained herein. While every precaution has been taken in the preparation of this book, the publisher assumes no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained herein.
Digital Electronics
Printed in the United States of America First Edition - First Printing 1990
ISBN 0-89704-049-X Library of Congress Catalog Card Number 90-83351
TABLE OF CONTENTS
Introductory Concepts...... 1
1.0Introduction...... 1
1.1Objectives...... 1
1.2Discussion ...... 2
1.2.0Digital and Analog Circuits ...... 2
1.2.1Use of Binary Digital Ones and 2 leros...... 5
1.2.2Digital Circuits...... 6
1.3Summary...... 8
1.4Review Questions ...... 8
Number Systems and Codes...... 11
2.0Introduction...... 11
2.1Objectives...... 12
2.2Discussion...... 12
2.2.0The Binary Number System ...... 13
2.2.1Binary to Decimal Conversion ...... 14
2.2.2Decimal to Binary Conversion ...... 14
2.2.3The Hexadecimal Number System ...... 15
2.2.4The Octal Number System ...... 16
2.2.5Binary Coded Decimal System ...... 16
2.2.6ASCII Code...... 17
2.3Summary...... 19
2.4Review Questions ...... 19
Logic Gates and Boolean Algebra...... 21
3.0Introduction...... 21
3.1Objectives...... 22
3.2Discussion ...... 22
3.2.0Boolean Variables ...... 22
3.2.1Truth Tables...... 23
3.2.2The OR Operation...... 24
3.2.3The AND Operation ...... 24
3.2.4The NOT Operation ...... 24
3.4.0Logic Equations...... 25
CHAPTER 1
CHAPTER 2
CHAPTER 3
in
CHAPTER 4
CHAPTER 5
3.2.6Logic Circuits...... 26
3.2.7NOR and NAND Gates ...... 28
3.3Summary...... 28
3.4Review Questions ...... 29
Lab Exercise 3.1 The NOT Circuit (Inverter) ...... 30
Lab Exercise 3.2 The AND Gate...... 33
Lab Exercise 3.3 The OR Gate...... 35
Lab Exercise 3.4 The NAND Gate ...... 36
Lab Exercise 3.5 The NOR Gate...... 37
Lab Exercise 3.6 Using NAND and NOR Gates ...... 38
Combinational Loj;;ic Circuits ...... 41
4.0Introduction...... 41
4.1Objectives...... 41
4.2Sum-of-ProductForm ...... 42
4.3Designing Combination Circuits ...... 42
4.4Boolean Sim plification ...... 44
4.5DeMorgan's Theorem ...... 45
4.6The Karnaugh Map...... 46
4.7Product-of-S urns Form ...... 51
4.8The Exclusive OR and Exclusive NOR Circuits .....54
4.9Summary...... 55
4.10Review Questions ...... 55
Lab Exercise 4.1 Minterm and Maxterm Truth Tables ....58
Lab Exercise 4.2 Simplifying Logic Circuits...... 61
Lab Exercise 4.3 Decoders...... 65
Lab Exercise 4.4 Encoders...... 68
Lab Exercise 4.5 Exclusive OR Circuits...... 69
Lab Exercise 4.6 The EXNOR Circuit...... 72
Flip-flops...... 75
5.0Introduction...... 75
5.1Objectives...... 76
5.2Discussion...... 76
5.2.0Set-Clear Flip-flops ...... 77
5.2.1The "D" Type Latch...... 79
5.2.2Clod; Signals...... 80
5.2.3Clocked "S-C" Flip-flops...... 81
5.2.4Clocked "T" Hip-flops ...... 82
5.2.5Clocked "D" Flip-flops...... 83
5.2.6"J-K" Flip-flops...... 84
IV
5.2.7Counting and Frequency Division ...... 86
5.2.8Monostable Multivibrators...... 87
5.3Summary...... 87
5.4Review Questions...... 88
Lab Exercise 5.1 Set-Clear Flip-flops...... 90
Lab Exercise 5.2 The "D" Latch ...... 93
Lab Exercise 5.3 The Clocked Set-Clear Filp-flops ...... 95
Lab Exercise 5.4 The "T" Flip-flops...... 97
Lab Exercise 5.5 The Clocked "D" Flip-flops; ...... 98
Lab Exercise 5.6 The "J-K" Flip-flops ...... 100
Lab Exercise 5.7 The One-Shot...... 102
Digital Arithmetic...... 105
6.0Introduction...... 105
6.1Objectives...... 105
6.2Discussion...... 106
6.2.0Binary Addition...... 106
6.2.1Signed Numbers...... 106
6.2.2Complement Notation...... 107
6.2.3Binary Multiplication...... 108
6.2.4Binary Division...... *...... 110
6.2.5Hexadecimal Arithmetic...... Ill
6.2.6BCD Addition...... Ill
6.2.7The Half-adder...... 112
6.2.8Full-adder...... 113
6.2.9Parallel Binary Adder...... 113
6.2.10BCD Adder...... 114
6.2.11Binary Multipliers ...... 115
6.3Summary...... 115
6.4Review Questions ...... 115
Lab Exercise 6.1 Binary Adders...... 117
Lab Exercise 6.2 Parallel Binary Adder...... 118
Lab Exercise 6.3 The BCD Adder...... 121
Lab Exercise 6.4 The ALU...... 123
Counters and Registers...... 127
7.0Introduction...... 127
7.1Objectives...... 127
7.2Discussion...... 128
7.2.0Ripple Counters...... 128
7.2.1MOD Counters...... 129
CHAPTER 6
CHAPTER 7
VI
CHAPTERS
7.2.2Down Counters...... 130
7.2.3Parallel Counters...... 131
7.2.4Parallel UP/DOWN Counter ...... 131
7.2.5Presetable Counters...... 132
7.2.6IC Binary UP/DOWN Counter ...... 133
7.2.7Counter Decoding...... 133
7.2.8Shift Registers...... 134
7.2.9Johnson Counter ...... 135
7.2.10Integrated Circuit Registers...... 136
7.3Summary...... 140
7.4Review Questions ...... 140
Lab Exercise 7.1 UP/DOWN Counters...... 143
Lab Exercise 7.2 Synchronous Counters ...... 145
Lab Exercise 7.3 IC Counters...... 146
Lab Exercise 7.4 Shift Registers...... 149
Lab Exercise 7.5 The 74165...... 152
Lab Exercise 7.6 The 74164...... 154
Integrated Circuit Logic Families...... 157
8.0Introduction...... ;...... '.....157
8.1Objectives...... *...... 157
8.2Discussion...... 158
8.2.0Terminology ...... 158
8.2.1TTL Logic Family...... 159
8.2.2Standard TTL Logic Characteristics...... 161
8.2.3TTL Loading Rules ...... 162
8.2.4Using Specification Sheets ...... 162
8.2.5Open Collector Outputs...... 164
8.2.6Three-State Logic...... 168
8.2.7Other TTL Families ...... 169
8.2.8The MOSFET...... 170
8.2.9CMOS...... 171
8.2.10Interfacing CMOS and TTL ...... 172
8.2.11ESD Control...... 173
8.3Summary...... 173
8.4Review Questions ...... 173
Lab Exercise 8.1 TTL Loading Rules ...... 175
Lab Exercise 8.2 Open-Collector Logic Gates...... 176
Lab Exercise 8.3 Three-State Logic ...... 177
Lab Exercise 8.4 TTL and CMOS Interfacing...... 179
Medium Scale Integration...... 181
9.0Introduction...... 181
9.1Objectives...... 181
9.2Discussion...... 181
9.2.0Decoders...... 182
9.2.1BCD-to-Decimal Decoder...... 182
9.2.2BCD-to-Seven Segment Display Decoders ....183
9.2.3Common Displays ...... 184
9.2.4Encoders...... 186
9.2.5Multiplexers ...... 187
9.2.6Demultiplexers...... 191
9.2.73-State Registers ...... 193
9.3Summary...... 193
9.4Review Questions ...... 193
Lab Exercise 9.1 Decoders...... 195
Lab Exercise 9.2 Decoder/Drivers...... 197
Lab Exercise 9.3 Encoders...... 199
Lab Exercise 9.4 Digital Multiplexers ...... 201
Lab Exercise 9.5 Demultiplexers...... 203
Data Conversion/Acquisition ...... 205
10.1 Introduction...... ,.205
10.1Objectives...... 205
10.2Discussion...... ,206
10.2.0D/A Conversion...... 206
10.2.1D/A Specifications...... 209
10.2.2D/A Applications...... 210
10.2.3A/D Conversion ...... 211
10.2.4Successive Approximation A/D...... 212
10.2.5Data Acquisition ...... 213
10.2.6Sample and Hold Circuits ...... 213
10.2.7Multiplexing...... 214
10.3Summary...... 215
10.4Review Questions ...... 216
Lab Exercise 10.1 D/A Converters...... 217
Lab Exercise 10.2 A/D Converters...... 219
Lab Exercise 10.3 The Analog Multiplexer ...... 221
Potpourri...... 225
11.0Introduction ...... 225
11.1Objectives...... 225
CHAPTER 9
CHAPTER 10
CHAPTER 11
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CHAPTER 12
APPENDIX
11.2Discusssion...... 226
11.2.0The 555 Timer...... 226
11.2.1Opto-Isolators...... 227
11.2.2DIP Relays...... 227
11.2.3Programmable Logic Devices ...... 228
11.3Summary...... 231
11.4Review Questions...... 231
Lab Exercise 11.1 The 555 Timer...... 232
Lab Exercise 11.2 DIP Relays...... 234
Lab Exercise 11.3 The Opto-Isolator...... 236
Lab Exercise 11.4 Implementing Logic Functions
with ROMS...... 238
Microcomputer Concepts...... 241
12.0Introduction...... 241
12.1Objectives...... 241
12.2What is a Microcomputer? ...... 242
12.2.0Organization of the Microcomputer ...... 243
12.2.1Interfacing...... 247
12.2.1.0 Parallel and Serial Data
Transmission ...... 249
12.2.2Programming ...... 251
12.2.2.0Machine Code...... 252
12.2.2.1Assembly Language...... 254
12.2.2.2High Level Language...... 255
12.3Summary...... 257
12.4Review Questions...... 257
Pinouts of ICs Used in the LK-1 Kit ...... 259
vui
FIGURE 1-1. FIGURE 1-2. FIGURE 1-3.
FIGURE 1-4. FIGURE 1-5.
FIGURE 2-1.
FIGURE 2-2. FIGURE 2-3.
FIGURE 2-4.
FIGURE 2-5. FIGURE 3-1. FIGURE 3-2. FIGURE 3-3. FIGURE 3-4. FIGURE 3-5.
FIGURE 3-6. FIGURE 3-7.
FIGURE 3-8. FIGURE 3-9. FIGURE 3-10A FIGURE 3-10B. FIGURE 3-11. FIGURE 3-12. FIGURE 4-1.
FIGURE 4-2. FIGURE 4-3. FIGURE 4-4.
FIGURE 4-5. FIGURE 4-6. FIGURE 4-7.
FIGURE 4-8.
Typical Analog Signals ...... 2
Typical Digital Signals or Words ...... 4
Comparison of Binary and Decimal
Numbers...... 6
Schematic Diagram of a Digital Switch ...6
BJT (Bipolar Junction Transistor)
Inverter...... 7
Structure of a General Positional
Number System...... 12
Converting 214 Decimal to Binary ...... 15
Binary to Hexadecimal Number
System Conversion ...... 16
Binary /Octal Number System
Conversions ...... 16
Decimal Number Coded in BCD ...... 17
Truth Tables...... 23
Truth Table for the OR Operation ...... 24
Logical AND Truth Table...... 24
Truth Table for the NOT Operation ...... 25
Schematic Symbols for Boolean
Equations...... 27
Designing Circuit from Logic Equations ...27
Schematic Symbols for NAND and
NOR Gates...... 28
IC Orientation and Pin Numbering ...... 31
Basing Diagram for 74LS04 IC...... 32
HIGH Pulse Circuit...... 32
LOW Pulse Circuit...... 32
Circuit Schematic...... 38
Circuit Schematic...... 39
Circuit Implementation of Minterm
Expression...... 44
A Simplified Alarm Logic Circuit ...... 45
DeMorgan's Theorem...... 45
Logic Expressions, Truth Tables and K-Maps for Two, Three and Four Input
Variables...... 46
Examples of Looping...... ■....48
K-Map Simplification Examples ...... 49
K-Map Applied to Ink Factory
Alarm Problem...... 50
Don't Care Conditions in K-Map
Simplification ...... 50
ILLUSTRATIONS
IX
x
FIGURE 4-9. FIGURE 4-10. FIGURE 4-11. FIGURE 4-12. FIGURE 4-13.
FIGURE 4-14. FIGURE 4-15. FIGURE 4-16. FIGURE 4-17. FIGURE 4-18. FIGURE 4-19. FIGURE 4-20. FIGURE 4-21. FIGURE 4-22. FIGURE 4-23. FIGURE 4-24. FIGURE 4-25. FIGURE 4-26. FIGURE 4-27. FIGURE 5-1. FIGURE 5-2. FIGURE 5-3. FIGURE 5-4. FIGURE 5-5. FIGURE 5-6. FIGURE 5-7. FIGURE 5-8. FIGURE 5-9 FIGURE 5-10. FIGURE 5-11. FIGURE 5-12. FIGURE 5-13. FIGURE 5-14.
FIGURE 5-15.
Examples of Prod uct-of-Sums Logic
Equation...... 51
Steps in Creating the Product-of-Sums
Logic Equation...... 52
Implementation of the Equations in
Figure 4-10...... 53
Logic Implementation Using
Universal Gates...... 53
The Exclusive OR Gate and Exclusive
NOR Gate...... 55
K-Maps...... 55
Outputs for XOR and XNOR Gates...... 57
Examples of Minterm Truth Tables ...... 58
Examples of Maxterm Truth Tables ...... 59
Truth Table for Lab Exercise 4.2...... 62
Step 7 Circuit Schematic ...... 63
Two Variable Karnaugh Map ...... 63
Schematic of a Simple Decoder ...... 66
Schematic for a One of Four Decoder .....66
Schematic for a Simple Encoder...... 68
EXOR Truth Table...... 70
EXOR Schematic #1 ...... 70
EXOR Schematic #2...... 71
The EXNOR Circuit ...... 73
OR Gate Latch...... 76
NOR Gate Latch...... 77
NOR "S-C" Flip-flop ...... 77
Basic NAND Latch...... 78
NAND"S-C" Latch ...... 79
NOR "D" Latch ...... 79
NAND "D" Latch ...... 80
Clocked "S-C" Hip-flop...... 81
Clocked "T" Flip-flop...... 82
Timing Diagram for "T" Flip-flop ...... 82
Clocked "D" Flip-flop ...... 83
"J-K" Flip-flop ...... 84
"J-K" Flip-flop Configurations ...... 85
"J-K" Master-slave Flip-flop Circuit
Diagram...... 85
Schematic Symbol for Edge Triggered
Flip-flop...... 90
FIGURE 5-16. FIGURE 5-17. FIGURE 5-18. FIGURE 5-19. FIGURE 5-20. FIGURE 5-21. FIGURE 5-22. FIGURE 5-23. FIGURE 5-24. FIGURE 5-25. FIGURE 6-1. FIGURE 6-2. FIGURE 6-3. FIGURE 6-4. FIGURE 6-5.
FIGURE 6-6. FIGURE 6-7.
FIGURE 6-8. FIGURE 6-9. FIGURE 6-10. FIGURE 6-11. FIGURE 6-12. FIGURE 6-13. FIGURE 6-14. FIGURE 6-15. FIGURE 6-16. FIGURE 6-17. FIGURE 6-18A. FIGURE 6-18B. FIGURE 6-19. FIGURE 7-1. FIGURE 7-2. FIGURE 7-3. FIGURE 7-4. FIGURE 7-5. FIGURE 7-6. FIGURE 7-7. FIGURE 7-8. FIGURE 7-9.
Edge Trigger Circuits...... 91
Schematic for NOR "S-C" Flip-flop ...... 91
Schematic for NAND "S-C" Flip-flop ....92
Schematic for "D" Flip-flop...... 93
Schematic for Clocked "S-C" Flip-flop ....96
Schematic for "T" Flip-flop ...... 97
Schematic for Clocked "D" Flip-flop ...... 99
"J-K" Flip-flop Schematic ...... 100
Schematic for Step Seven...... 101
"One-Shot" Schematic ...... 102
Rules of Binary Addition ...... 106
Example of Signed Numbers ...... 106
Rules for Binary Subtraction...... 107
Examples of Complement Notation ...... 107
Subtraction Using Two's Complement
Notation...... 108
Example of Multi-Digit Binary
Multiplication...... 109
Alternate Method for Multiplying Binary
Numbers ...... 109
Alternate Method for Division ...... 110
Binary Division by the Restoring Method ..Ill
BCD Addition Examples...... Ill
Half-Adder...... 112
Full-Adder...... 113
Parallel Adder IC...... 114
BCD Adder Circuit...... 114
Half-Adder Schematic...... 117
Full-Adder Schematic ...... 118
Parallel Binary Adder Circuit...... 119
BCD Adder Circuit...... 122
Display Circuit...... 122
74181 Adder...... 124
Examples of Ripple Counters ...... 128
Count Rate Formula ...... 129
Clock and Strobe Pulses...... 129
Examples of Down Counters...... 130
Parallel Counter Circuit ...... ,131
Parallel Up/Down Counter ...... 132
Presetable Counter...... 133
"J-K" Hip-flop Shift Register ...... 134
"D" Hip-flop Shift Register...... 135
XI
Xll
FIGURE 7-10. FIGURE 7-11. FIGURE 7-12. FIGURE 7-13. FIGURE 7-14. FIGURE 7-15. FIGURE 7-16. FIGURE 7-17. FIGURE 7-18A. FIGURE 7-18B. FIGURE 7-19. FIGURE 7-20. FIGURE 7-21. FIGURE 7-22. FIGURE 7-23. FIGURE 8-1. FIGURE 8-2. FIGURE 8-3. FIGURE 8-4. FIGURE 8-5. FIGURE 8-6. FIGURE 8-7. FIGURE 8-8. FIGURE 8-9. FIGURE 8-10. FIGURE 8-11. FIGURE 8-12. FIGURE 8-13. FIGURE 8-14. FIGURE 9-1. FIGURE 9-2. FIGURE 9-3.
FIGURE 9-4. FIGURE 9-5. FIGURE 9-6. FIGURE 9-7.
FIGURE 9-8. FIGURE 9-9.
FIGURE 9-10.
Johnson Counter ...... 136
74174 Logic Diagram...... 137
74174 PIPO Shift Register...... 138
7494 Logic Diagram...... 139
74165 Logic Diagram...... 139
74164Logic Diagram...... 140
Up Counter...... 143
Synchronous Up Counter ...... 145
Decade Counter...... 147
Seven Segment Display...... 147
4-Bit Binary Up/Down Counter ...... 148
SISO Shift Register...... 150
74174 PIPO Shift Register...... 151
74165PISO Shift Register...... 153
74164 SIPO Shift Register ...... 154
Typical Pulse Signal ...... 158
Diode Logic Gates...... 160
Basic TTL Circuit...... 160
Sinking and Sourcing Current ...... 161
Simple Inverting Amplifier Output ...... 164
Totem-Pole Output Amplifier ...... 165
Open Collector TTL Gate...... 166
Examples of Wired Logic ...... 166
Three-State Logic ...... 168
Schottky Barrier Diode Circuits ...... 169
MOSFET Construction ...... 170
Methods of Interfacing TTL and CMOS ....172
CMOS/TTL Interfacing ...... 180
TTL/CMOS Interfacing ...... 180
BCD to Decimal Decoder Logic Diagram ...182
Seven-Segment Display Labeling ...... 183
Logic Diagram BCD to Seven Segment
Decoder-Driver IC...... 184
Decimal to BCD Encoder...... 186
8-Line to 3-Line Priority Encoder ...... 187
Simple Multiplexer Logic Diagram ...... 188
Parallel to Serial Conversion Using a
Multiplexer ...... 188
8-Input MUX Logic Diagram ...... 189
Multiplexer Used as a Boolean Function
Generator...... 190
Simple Demultiplexer ...... 191
FIGURE 9-11.
FIGURE 9-12. FIGURE 9-13. FIGURE 9-14. FIGURE 9-15. FIGURE 9-16.
FIGURE 10-1. FIGURE 10-2. FIGURE 10-3. FIGURE 10-4. FIGURE 10-5. FIGURE 10-6.
FIGURE 10-7. FIGURE 10-8. FIGURE 10-9. FIGURE 10-10 FIGURE 10-11 FIGURE 10-12 FIGURE 11-1. FIGURE 11-2. FIGURE 11-3. FIGURE 11-4. FIGURE 11-5. FIGURE 11-6. FIGURE 11-7. FIGURE 11-8. FIGURE 11-9. FIGURE 12-1. FIGURE 12-2. FIGURE 12-3. FIGURE 12-4. FIGURE 12-5.
Serial to Parallel Conversion Using
a Demultiplexer ...... 192
BCD/DEC Decoder...... 196
BCD/7-Segment Decoder ...... 198
8-Line to 3-Line Encoder ...... 200
Simple Multiplexer ...... 202
Simple Demultiplexer ...... 203
Basic D/A Converter Block Diagram .....206
Simple D/A Converter ...... 207
Binary Ladder D/A Converter ...... 208
Ladder Analysis for A4...... 209
Flash A/D Converter ...... 211
Successive Approximation A/D
Converter ...... 212
Sample and Hold Circuit...... 213
Rotary Switch ...... 214
Typical Data Acquisition Systems ...... 215
. Simple D/A Converter ...... 218
. A/D Converter...... 220
. MUX Circuitry...... 222
555IC Basing and Circuit Diagrams ...... 226
PAL Architecture ...... 228
ROM Architecture ...... 229
PCA Architecture...... 230
One-Shot Circuit ...... 232
Astable Circuit...... 233
DIP Relay...... 234
Opto-Isolator TTL /CMOS Converter...... 236
Programming Circuit ...... 238
Computer Families ...... 242
Generalized Microcomputer ...... 244
Parallel Port Functional Diagram ...... 249
Serial Port Functional Diagram ...... 250
Industry Standard Data Bus Definitions ....251
Xlll
TABLES
TABLE 2-1. TABLE 2-2.
TABLE 2-3.
TABLE 2-4. TABLE 2-5. TABLE 3-1. TABLE 4-1. TABLE 4-2. TABLE 8-1. TABLE 8-2. TABLE 8-3. TABLE 9-1. TABLE 11-1.
Structure of the Binary Number System ...14
Converting 11010110 Binary to
Decimal 214...... 14
Additional Digits for the Hexadecimal
System...... 15
Excess-3 BCD Code...... 17
ASCII Code...... 18
Basic Laws of Boolean Algebra...... 26
Truth Table and Minterm Expression .....43
Boolean Theorems ...... 44
TTL Characteristics...... 161
Typical TTL Parameters...... 164
CMOS Logic Characteristics...... 171
Boolean Products of an 8-Bit Multiplexer ..190
Data Table...... 239
xiv
WARNING
FEDERAL REGULATION (PART 15 OF FCC RULES)
PROHIBITS THE USE OF COMPUTING EQUIPMENT
WHICH CREATES RADIO OR TV INTERFERENCE
Interplex Electronics specifically warns the user of this instrument that it is intended for use in a classroom or laboratory environment for the purpose of learning and experimentation. When building experimental circuits, it may emit interference that will effect radio and television reception and the user may be required to stop operation until the interference problem is corrected. Home use of this equipment is discouraged since the likelihood of interference is increased by the close proximity of neighbors.
CORRECTIVE MEASURES:
Interference can be reduced by the following practices.
1)Install a commercially built RFI power filter in the power line at the point where the cord enters the unit.
2)Avoid long wires. They act as antennas.
3)If long wires must be used, use shielded cables or twisted pairs which are properly grounded and
terminated.
xv
XVI