Although There Is No Way to Develop Silicon IP That Can Be Used in Different Designs With

0805DotOrg.doc

Keywords: IP, quality, reuse, integration, VSIA

@head:IP Aggregation Drives Successful IP Reuse

@deck:By helping IP providers and integrators assess IP quality, aggregators can ensure reusability while minimizing customer modification for different chips.

@text:Integrating IP is rapidly becoming the biggest challenge for ASIC designers. There is simply no way to develop fully reusable hard or soft silicon IP of any reasonable complexity so that system-on-a-chip (SoC) developers could reuse unmodified IP in different designs. The wide variety of design environments, tool sets, and chip test requirements make this goal impossible to achieve.

Yet there is a way to minimize the work that IP integrators must do to reuse that IP. To achieve a detailed ranking for the IP while simplifying reuse, it’s vital to carefully evaluate and assure the quality of the IP with the design tools and within the design environment that the IP integrator will use. Unfortunately, this technique for maximizing IP reusability is very time consuming and expensive.

Smaller IP developers find it difficult to spend the time and money needed to make their product “bulletproof.” After all, they have to sell their IP at competitive prices. Big IP vendors have a problem qualifying what is usually a wide range of products. On the IP user side, most integrators don’t have enough time or resources to verify IP reusability for the multiple IP cores that typically go into each chip that they develop. Typically, these users won’t fully qualify IP for a specific application until it is needed for that purpose. This approach can seriously impact their chip delivery schedules.

The solution is an IP-aggregation organization that works closely with IP vendors, silicon foundries, EDA companies, IP integrators, and test facilities. Such an aggregator can make sure that each IP core is qualified with the proper process models, EDA tools, and design methodologies for each target silicon process and tool suite. As a result, it will be possible to maximize the IP reusability for a range of cores and IP customers. Through economies of scale, the aggregator can cost effectively develop and employ IP rating procedures and a quality-assurance (QA) platform. This platform will maximize the usefulness of the IP for many applications with minimal user intervention and modification. In addition, this approach has a positive impact on chip reliability and performance predictability.

An aggregator like Open-Silicon works with both IP providers and the company’s customers--the IP integrators--to assure IP quality and reusability. The aggregator also helps to ensure first-time working silicon. To accomplish this goal, a customer’s needs are ascertained for every hard IP core in the aggregator’s portfolio. The next step is to determine whether it is strategic to add the IP to the aggregator’s portfolio for future deployment with other customers (see Figure).

The key person for IP identification and evaluation is an engineer who is knowledgeable about the type of IP being considered. This engineer is the key technical contact for perspective IP vendors.

The IP engineer determines the type of IP core to add to the aggregator’s library based on projected customer requirements and strategic considerations. He or she then talks to several potential IP vendors. At this stage, the goal is to narrow the choice to a qualified preferred vendor and backup vendors. The engineer/vendor discussion is technology driven. The aggregator gives the vendor an IP-deliverable checklist comprising guidelines and file requirements. That checklist contains the required IP integration files, a directory structure with file-format considerations, and a list of design collateral for that IP.

To run design-tool suites, the integrator needs IP collateral like Verilog source code, timing, placement, GDS II, Spice netlist schematics, and test models. The design collateral includes the following: the targeted process and foundry, design-rule document, technology file, DRC/LVS command file, process modes, and characterization conditions for the IP.

After receiving the IP collateral from the vendor, the aggregator’s engineer will review it to see if what they have received matches the checklist requirements. The engineer then performs several tasks to see if the IP meets the aggregator’s acceptance requirements. These tasks include:

1. Checking file correlation

2. Running the recommended tool suites (Magma or Synopsys) to instantiate the IP while keeping an eye out for IP/design-tool incompatibilities

3. Running Spice to verify the IP’s timing

As part of the IP verification process, companies like Open-Silicon have a system in place to do configuration checks of tools, foundry models, tool scripts, and its own scripts (which it uses to automate the IP flow process). Any dependency change triggers a flag that requires re-verification of the flow. If any incompatibilities are found from the re-verification, they can be presented to the IP vendor for correction. An example of a problem that might appear would be the availability of a new foundry Spice file. If the IP vendor hasn’t changed the IP collateral to reflect the new model, the aggregator should spot the inconsistency.

Aside from its role as a verifier of IP quality, a third-party IP aggregator substantially reduces the legal and sales costs that are usually imposed upon an IP integrator when licensing IP. The aggregator can put a contract in place with the provider for each particular piece of IP. Each customer contract covers everything--including all of the IP for the customer’s design. This approach can substantially reduce the cost of the IP for the integrator, who gets qualified IP without having to endure an expensive and time-consuming procurement process.

As the need for quality and evaluation metric mechanisms increases for both IP vendors and integrators, organizations like the FSA and VSIA are introducing IP subcommittees and tools. An example is the VSIA’s Quality IP Metric (QIP). The organizations’ goal is to put industry-wide IP-quality mechanisms in place.

IP aggregation is a win-win situation for both the IP provider and integrator. The IP vendors receive quality, compatibility, and configuration checks on their products. Usually, these checks go beyond what they have the financial and manpower resources to do for every core that they offer. The IP integrators get a piece of IP that is fully checked for use in their design and tool environments. It also is at a level of verification that the customers cannot obtain by themselves. The result is IP that is reuse-ready. It requires a minimum of customer modification for different chips.

Elias Lozano (left) is the Senior IP and Analog Manager for Open-Silicon. He helps procure and qualify a wide variety of analog, mixed-signal, and digital
IP. Lozano has over 15 years of specialized experience in analog, mixed-signal, and digital design.
Rajesh Shah (right) is the Director of Engineering and IP for Open-Silicon. He works closely with customers on architecture benefit analysis to help optimize their IP integration. Shah received his MSEE from the University of Texas at Austin.

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Captions:

The IP integrator uses this procedural flow to assess the vendor IP type and quality.