Tirkel and Rabinowitz

Modeling Quality versusFlow Time due toInspections

I. TirkelandG. Rabinowitz

Industrial Engineering and Management, Ben-Gurion University of the Negev

P.O.B. 653, Beer-Sheva 84105

ABSTRACT

Modern industry strives forboth high Quality and short FlowTime, yet practice and researchrarely consider them simultaneously. Weinvestigate the effect of in-line inspection on Quality and FT.This work relies on analytical and simulation analysis of a Production Cell model, which represents a short segment of a typical production-line. Various inspection frequencies and scheduling areapplied viaa known static inspection policy and two dynamic policies.Results indicate that contrary to common intuition,the best Quality results are not achieved for the highest inspection frequency, but rather for the policy that balances well between average frequency and information turn.Similarly, best results are not achieved for the highest inspection tool utilization. The proposed dynamic policies achieve superior performance to the common static policy.Also shown is that perceived Quality is usually worse than actual Quality.

  1. INTRODUCTION

Semiconductors industry strives for high Quality and short Flow Time (FT) since both have significant impact profit. High Quality increases revenue (e.g. salable output, market share)and decreases cost per unit, andshort FT reduces costs (e.g. inventory) and increases revenue(e.g. response to customer). Practice and research usually consider Quality and FT separatelyand focus mostly on FT, for example: Kao and Chou [1], Lozinski and Glassey [2], Sandell and Srinivasan [3]. Literature considering both usually relieson the known premise that assumes Quality deteriorates with longer FT, for example: Khetan and Fowler [4], Meyersdorf and Yang [5], Wein[6]. Even less common is literature that investigates the relationship empiricallyyetdoes not to establish a model, for example:Chang etal. [7], Cunningham and Shanthikumar [8], Leachman etal. [9]Srinivasanetal. [10].

We attempt to investigate and model Quality and FT relationship as affected by operational factors. Many of these factors (e.g. maintenance, machine rate, inspection policies) impact both Quality and FT, some of which are contradicting as illustrated in Fig. 1. In order to limit the complexity caused by the inter-factors interactions, we investigate the effect of in-line inspection frequency and scheduling (shaded in Fig. 1) on both Quality and FT simultaneously. The goal of this work is to establish analytical and simulation models for studying the relationship between Quality and FT in a randomly deteriorating production system due to in-line inspection scheduling. Although the study is motivated by semiconductors wafer fabricationwhich relies heavily on in-line inspection, per Mittal and McNally [11], it is applicable to other industries.

Fig. 1: Factors effecting Quality and FT

  1. MODEL AND METHODOLOGY

A short production-line segment is modeled by a Production Cell which consists of two production steps namedFeeder and Bleeder, and one inspection step namedMetro. Each step is represented by a single queue. Product-items are routed either directly from the Feeder to the Bleeder, or from the Feeder through the Metro inspection first and then to the Bleeder, as illustrated in Fig. 2.

Fig. 2: The Production Cell

The Quality modeling is based on Duncan [12] due to its simplicity and applicability,used for example by:Nurani etal. [13] and Del Castillo and Montgomery [14]. TheFeeder's state randomly deteriorates from in-control (IC) to out-of-control (OOC) with a known and fixed probability, and only with external intervention it is immediately restored back to IC. Following a pre-defined Inspection Policy (IP), an item is sent to be inspected in Metro and is correctly detected as I-OOC (Item processed by OOC Feeder) or as I-IC (Item processed by IC Feeder). Thus, the model can measure quality in %I-OOC, which can also be easily related to Yield. An I-OOC item has lower expected Yield than an I-IC, yet both yields are fairly high and hence are inspected for monitoring the Feeder’s state only and not for scrapping. The Feeder'sQuality modeling is illustrated in Fig. 3.

Fig. 3: Feeder's Quality modeling

Three IP's, one predictive (static) and two reactive (dynamic), as classified by Metha and Uzsoy [15] and Ouelhadj and Petrovic [16], are usedwith different parameters and evaluated as follows: (i) Fixed Measure Rate (FMR),the static and most common IP,where every xth itemis sent to inspection; various x values were analyzed. FMR was investigated analytically and compared (via simulation) versus two other proposed dynamic IPs. (ii) where an item departing the Feeder is sent to inspection if the Metrosystem has Less Than x items and the Bleederhas More Than yitems (MLT&BMT); various (x,y) values were analyzed. (iii) whenMetrobecomes Empty it inspects the Freshest Item (last one departed the Feeder) (ME&FI).

  1. RESULTS AND ANALYSIS

The analytical model analysis of FMR resultedin identifying and isolating two variablesthat impact on Quality and FT, as follows:

a)Measure Cycle (MC) –the number of items between two consecutive items sent to inspection by Metro.

b)Information Turnaround (IT) –the time duration from sending an I-OOC item to inspection byMetroand untilthe correction feedback reaches the Feeder.

Based on this analysis we were able to identify that each inspection policy created different combinations ofMC and IT, and thus had different impact on Quality and FT. The simulation model used for the results is based on Tirkel et. al. [17].

FT grows with inspection frequency, generated by lower MC. Quality increases with inspection frequency but also with reduced IT. Yet, lower MC causes increased IT, as illustrated by Fig. 4. Notice this relationship is different among the IPs.

Fig. 4: IT versus MC tradeoff, under different IP's

Each IP,per its specific assignment of parameters, creates a different relationship curve for MC and IT. Thus, each IP also differently affects Quality and FTand creates a different curve as a result, as illustrated in Fig. 5.

Fig. 5: Quality as measured by %I-OOC versus FT, under different IP's

At higher inspection frequencies, as generated by lower MC, the Metro inspection toolutilization is higher. Clearly, since each IP works with different MC it also utilizes the Metrotool differently. Fig. 6 illustrates Quality versus Metro tool utilization under different IPs. Notice that the highest utilization does not generate the highest Quality, just as the lowest MC doesn't do it.

Fig. 6: %I-OOC versus Metro tool Utilization, under different IP's

The last result showsthecomparison between %I-OOC (of all the produced items)and%II-OOC (of inspected items, the available data in practice), under FMR policy. Fig. 7 illustrates the gap between levels of perceived Quality (measured by %II-OOC) versus actual Quality (measured by %I-OOC). Notice the gap grows with lower FT (at lower MC).

Fig. 7: %I-OOC (all items) and %II-OOC (inspected items) versus FT, under FMR

  1. CONCLUSIONS

Conclusions deducted from analyzing the results, are as follows:

  1. Lower MC increases FT since moreitems are inspected and each spends more time (IT) at the higher loaded Metro.
  2. On the other hand, lower MC reduces%I-OOC thuspresenting a tradeoff (versus higher FT), till %I-OOC starts to increase (Fig. 5)due toinflating IT(Fig. 4).
  3. Different policies, for a given MC, generate unlike effects on IT (Fig. 4), and consequently create different Quality versus FT curves (Fig. 5).
  4. For the same FT, the dynamic policies illustrate lower %I-OOC making them preferred over FMR (Fig. 5).
  5. Lowest %I-OOC and itsMetroutilization highly dependent on the IP (Fig. 6).
  6. %II-OOC is either the same or higher than %I-OOC (shown under FMR). Since in practice %II-OOC is known,ignoring this difference may bias upward the estimated%I-OOC and the Yield loss (Fig. 7).
  1. REFERENCES
  1. C. E. Kao, Y. C. Chou,A Tool Portfolio Planning Methodology for Semiconductor Wafer Fabs,Semiconductor Manufacturing Technology Workshop, 84-90, 2000.
  2. C. Lozinski, C. R. Glassey, Bottleneck Starvation Indicators For Floor Shop Control,IEEE Transactions on Semiconductor Manufacturing, 1(4), 147-153, 1998.
  3. R. Sandell, K. Srinivasan, Evaluation of Product Release Policies for Semiconductor Manufacturing Systems,Proceedings of the 28th conference on Winter simulation, 1014-1022, 1996.
  4. S. Khetan, P. Fowler, Managing High IC Yields with Short Cycle Times,Gallium Arsenide Integrated Circuit Symposium, 119-123, 1995.
  5. D. Meyersdorf, T. Yang, Cycle Time Reduction for Semiconductor Wafer Fabrication Facilities,IEEEISEMI Advanced Semiconductor Manufacturing Conference, 418-423, 1997.
  6. L. M. Wein, On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication,IEEE Transactions on Semiconductor Manufacturing, 2(2), 156-158, 1992.
  7. W. C. Chang, M. Yu, R. Wu, C. Chen, J. Chen, C. Y. Hsieh, C. K. Wang, Yield Improvement through Cycle Time and Process Fluctuation Analyses,2001 IEEE International Semiconductor Manufacturing Symposium, 267-270, 2001.
  8. S. P. Cunningham, J. G. Shanthikumar, Empirical Results on the Relationship Between Die Yield and Cycle Time in Semiconductor Wafer Fabrication,IEEE Transactions on Semiconductor Manufacturing, 9(2), 273-277, 1996.
  9. R. C. Leachman, D. Shengwei, C. Chen-Fu, Economic Efficiency Analysis of Wafer Fabrication,IEEE Transactions on Automation Science and Engineering, 4(4), 501 – 512, 2007.
  10. K. Srinivasan, R. Sandell, S. Brown, Correlation between Yield and Waiting Time: A Quantitative Study,IEEE/CPMT Int Electronics Manufacturing Technology Symposium, 65-69, 1995.
  1. S. Mittal, P. McNally, Line Defect Control to Maximize Yields,Intel Technology Journal, Vol. 4(2), 1998.
  2. A. J. Duncan, The Economic Design of X-Charts used to Maintain Current Control of Process,Journal of the American Statistical Association, 51(274), 228-242, 1956.
  3. E. Del Castillo, C. Montgomery, A General Model for the Optimal Economic Design of X-Bar Charts used to Control Short or Long Run Processes, IIE Transactions, 28(3), 193-201, 1996.
  4. R. K. Nurani, R. Akella, A. J. Strojwas,In-line defect sampling methodology in yield management: an integrated framework.IEEE Transactions on Semiconductor Manufacturing, 9(4),506-517, 1996.
  5. S. V. Metha,R. Uzsoy, Predictable Scheduling of a Single Machine Subject to Breakdowns,International Journal of Computer Integrated Manufacturing,12(1), 15-38, 1999.
  6. D. Ouelhadj, S. Petrovic, A Survey of Dynamic Scheduling in Manufacturing Systems, Journal of Scheduling, 12(4), 417-431, 2009.
  7. I. Tirkel, N. Reshef, G. Rabinowitz, In-line Inspection Impact on Cycle Time and Yield,IEEE Transactions on Semiconductor Manufacturing, 22(4), 491-498, 2009.