A SCALABLE AND MODULAR ARCHITECTURE FOR HIGH-PERFORMANCE PACKET CLASSIFICATION

ABSTRACT:

Packet classification is widely used as a core function for various applications in network infrastructure. With increasingdemands in throughput, performing wire-speed packet classification has become challenging. Also the performance of today’spacket classification solutions depends on the characteristics of rulesets. In this work, we propose a novel modular Bit-Vector (BV)based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA). We introduce analgorithm named StrideBV and modularize the BV architecture to achieve better scalability than traditional BV methods. Further, weincorporate range search in our architecture to eliminate ruleset expansion caused by range to-prefix conversion. The postplace-and-route results of our implementation on a state-of-the-art FPGA show that the proposed architecture is able to operate at100+ Gbps for minimum size packets while supporting large rulesets up to 28 K rules using only the on-chip memory resources.Our solution is ruleset-feature independent, i.e. the above performance can be guaranteed for any ruleset regardless the compositionof the ruleset.

EXISTING SYSTEM:

PACKET classification is a prominent technique used innetworking equipment for various purposes. Its applicationsare diverse, including network security, accesscontrol lists, traffic accounting. Toperform packet classification, one or more header fields ofan incoming packet is checked against a set of predefinedrules, usually referred to as a ruleset or a classifier.Performing packet classification is challenging since itinvolves inspection of multiple fields against a ruleset possibly containing thousands of rules. Performing suchoperations at wire-speed is even more challenging with theincreasing throughput demands in modern networks. Varioushardware platforms have been employed for packetclassification in the past.

DISADVANTAGES OF EXISTING SYSTEM:

Optimizations that target a specific ruleset feature,are not robust to be employed in environments where theruleset changes dynamically and frequently.

Various hardware are required to do efficiently.

PROPOSED SYSTEM:

We present a novel architecture for packetclassification, whose performance is independent fromruleset features and is suitable for hardware platforms.Weuse a Bit-Vector (BV) based approach to represent theruleset. Each rule is represented as a collection of sub-rulesand we propose an algorithm named StrideBV to generatethe sub-rules, which is an extension of the Field Split BitVector (FSBV) algorithm proposed in [6]. Our solutionoffers the user the flexibility of deciding the bit width ofeach sub-rule, which in turn decides the performancetrade-off of the architecture. In order to handle thearbitrary ranges,

we augment the architecture with explicitrange search capability which does not require any rangeto-prefix conversion. This yields higher memory efficiencywhich enhances the scalability of our approach. Inaddition, we propose a rule priority based partitioningscheme which allows us to modularize our solution toeliminate the inherent performance limitations in thetraditional BV approaches.

ADVANTAGES OF PROPOSED SYSTEM:

Itdelivers highperformance due to the custom built nature of the architectures.

A memory-efficient bit vector-based packet classificationalgorithm suitable for hardware implementation.

SYSTEM CONFIGURATION:-

HARDWARE REQUIREMENTS:-

Processor-Pentium –IV

Speed-1.1 Ghz

RAM-512 MB(min)

Hard Disk-40 GB

Key Board-Standard Windows Keyboard

Mouse-Two or Three Button Mouse

Monitor-LCD/LED

SOFTWARE REQUIREMENTS:

Operating system:Windows XP.

Coding Language:JAVA

Data Base:MySQL

Tool:Netbeans.

REFERENCE:

Thilan Ganegedara, Weirong Jiang, and Viktor K. Prasanna,“A Scalable and Modular Architecture forHigh-Performance Packet Classification”IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 25, NO. 5, MAY 2014.