The Off-Detector Opto-electronics for the Optical Links of the ATLAS SemiConductor Trackerand Pixel Detector
M.L. Chu, S.-C. Lee, D.S. Su, P.K. Teng
Institute of Physics, Academia Sinica, Taiwan
M. Goodrick
Cavendish Laboratory, Cambridge University, UK
N. Kundu, A.R. Weidberg[i]
Physics Department, Oxford University, UK
M. French, C.P. Macwaters, J. Matheson
Rutherford Appleton Laboratory, UK
Abstract
The off-detector part of the optical links for the ATLAS SCT and Pixel detectors is described. The VCSELs and p-i-ndiodes used and the associated ASICs are described. A novel array packaging technique is explained and an analysis of the performance of the arrays and the overall system performance is given. The proposed procedure for the set-up of the optical links in ATLAS is described.
PACS: 42.88, 04.40N, 85.40, 85.60.
Keywords: LHC; Optoelectronics; Data transmission; ASICs.
1.Introduction
Optical links will be used in the ATLAS SemiConductor Tracker (SCT) and Pixel detector[[1],[2]] to transmit data from the detector modules to the off-detector electronics and to distribute the Timing, Trigger and Control (TTC) data from the counting room to the front-end electronics[[3]]. This paper describes the performance of final prototypes of the off-detector opto-electronics. The main aim of this work was to verify the performance of the full system before starting the final production and to understand the procedures required to set up the optical links at the start of ATLAS operation.
The on-detector components are described in references [[4],[5],[6],[7]]. The overall system architecture of the SCT optical links is reviewed briefly in Section 2. The specifications for the VCSELs and p-i-n diodes are given in Section 3.The array packaging is a custom development, since no commercial MT coupled arrays are currently available. This development is therefore of potential interest to other applications involving many channels of fibre readout. The array packaging is described in Section 3. The ASICs used in the optical links are briefly reviewed in Section 4. The performance of the arrays and the combined performance of the arrays and ASICs were studied and the results are discussed in Section 5. The operation of the VCSEL driver ASIC to allow the minimisation of the jitter of the recovered 40 MHz bunch crossing signal is described.The proposed procedures to be used for the set-up of the system when installed in the ATLAS detector are described in Section6. Finally some conclusions are given in Section 7.
2.System Architecture and Specifications
The overall architecture of the SCT optical links is described in [1] and [3] and is briefly reviewed here for convenience. The system is illustrated schematically in Figure 1 below.
Figure 1 The ATLAS SCT optical links system architecture.
The links are based on GaAs VCSELs[ii] emitting light around 850 nm and epitaxial silicon p-i-ndiodes. There are 12 ABCD ASICs[[8]] on each SCT[1] module and each ABCD reads out the signals from 128 channels of silicon strips. The ABCD ASIC consists of 128 channels of preamplifiers and discriminators. The binary data from each channel is stored in a pipeline memory and the binary data corresponding to a first level trigger (L1) signal is read out. Two data links operating at 40 Mbits/s transfer the data from the ABCD ASICs on each SCT module to the off-detector opto-electronics. The ABCD ASICs[1] send the data to the VDC ASIC[6] which drives two VCSEL channels[4]. The data is sent in NRZ[iii] format via radiation hard optical fibre[7] to the p-i-ndiode arrays in the Back of Crate (BOC) card[iv] in the counting room. The electrical signals from the p-i-ndiode arrays are discriminated by the DRX-12 ASIC which provides LVDS[v] data used in the SCT Read Out Driver (ROD).
Optical links are also used to send the TTC data from the RODs to the SCT modules. The BPM-12 ASIC uses biphase mark (BPM) encoding to send a 40 Mbits/s control stream in the same channel as the 40 MHz Bunch Crossing (BC) clock. The outputs of the BPM-12 ASIC drive an array of 12 VCSELs which transmit the optical signal into 12 radiation hard fibres[7]. The signals are converted from optical to electrical by the on-detector p-i-ndiodes[5]. The electrical signals from the p-i-ndiodes are received by the DORIC4A ASIC[6] which discriminates the signal and decodes the BPM data into a 40 MHz BC clock and a 40 Mbit/s control data stream. The output stages translate the BC clock and control data into LVDS signals.
The architecture of the optical links for the Pixel system is described in Ref.[2]. The Pixel system uses essentially the same components for the off-detector end of the optical links as the SCT. The one minor difference is that the Pixel system will use 8- way arrays, whereas the SCT uses 12-way arrays. The data links for the innermost layer (“B layer”) of the Pixel system will be operated at 80 Mbits/s while the other layers will be operated at the same speed as those for the SCT. The studies described in this paper focussed on the SCT operation at 40 Mbits/s, although given the measured speed of the links the operation at 80 Mbits/s is not expected to pose any problems.
2.1System Specifications
Single bit errors will cause the loss of valid hits from the silicon detectors or the creation of spurious hits. The upper limit on the Bit Error Rate (BER) is specified as 10-9, as an error rate at this level would give a negligible contribution to the detector inefficiency or to the rate of spurious hits. In practice the error rate in the system has been measured to be much lower than this value (see Section 5.1.2). Since the system involves 8176 data links, it should be simple to set-up and operate with minimum adjustments. Therefore, it is important that the system should work with low BER over a wide range of the adjustable parameters.
The specifications for the TTC links from the ROD to the detector are given in Table 1below.
Table 1 Specifications for the TTC links.
Parameter / Minimum / Typical / Maximum / UnitsBER / - / <10-11 / 10-9 / -
Jitter of recovered clock (RMS) / - / 0.1 / 0.5 / ns
Single bit errors can cause a loss of level 1 triggers and it has been evaluated that a BER of 10-9 would cause a negligible loss of data[[9]]. At high luminosity a BER of ~ 10-10 is expected due to Single Event Upsets[9]. The actual BER for the TTC links have also been measured to be much lower (see Section 5.3.3). The requirement on the jitter of the recovered clock is based on not degrading the efficiency of the binary system used for the readout of the SCT detectors[1]. The tight specification on the timing jitter of the recovered bunch crossing clock arises from the need to assign hits in the detector to the correct bunch crossing while allowing for the time walk of the signal from the front-end electronics. As for the data links, it is important that a low BER can be achieved for the TTC links, over a wide range of the adjustable parameters.
3.VCSEL and p-i-narrays
3.1p-i-n Arrays
Arrays of silicon p-i-ndiodes are used to receive the readout data from the front end modules. Epitaxial silicon p-i-ndiodes[vi] are used because the i layer provides a thin active layer allowing for fast operation at low p-i-n bias voltage. The manufacturer’s specifications for the p-i-narray are given in Table 2below.
Table 2 Specifications for the p-i-narrays.
Characteristics / Min. / Typical / Max. / UnitsOperating wavelength / 820 / 840 / 860 / nm
Input optical power / 1 / 3 / mW
Responsivity @ 820 –860 nm and 5V bias / 0.4 / 0.5 / A/W
Dark current / <1 / 2 / nA
Reverse voltage / 5 / 10 / V
Breakdown voltage / 15 / 20 / V
20%-80% Rise/Fall time at 5V bias / 1 / 2 / ns
Temperature range / 10 / 20 / 50 / °C (condition for package not chip)
The active area of each individual p-i-ndiode is circular with a diameter of 130 mand the depth of the iregion is 35 m.
3.2VCSELs
VCSELs [[10]] are used to transmit the TTC signals to the front end modules optically. The main advantages of VCSELs are that they provide large optical signals at very low currents and have fast rise and fall times. In order to lower the laser threshold current, VCSELs use ion implants to selectively produce a buried current-blocking layer to funnel current through a small area of the active layer[[11]]. In older VCSELs this current confinement was achieved with proton implants. The VCSELs[vii] used in this study havean oxide implant to achieve the current confinement, which is becoming the standard VCSEL technology as it produces lower thresholds and higher bandwidth.The one disadvantage for this application with the oxide confined VCSELs was the relatively large opening angle (the FWHM of the emitted radiation for these VCSELs[viii] is 150). This results in a very low coupling efficiency into the 50 m core step index multi-mode (SIMM) fibre if no lens is used. In order to achieve a higher coupled power into the SIMM fibre without the complication of the use of a lens, a special production run was made with a lower reflectivity of the emitting surface which results in a slightly higher threshold but a much larger slope efficiency. The threshold increase was rather small (~ 1mA) but there was a big increase in slope efficiency which results in a much higher optical power at a nominal drive current of 10 mA. Therefore, it was possible to obtain a typical fibre coupled power of greater than 1 mW at a drive current of 10 mA. This optical power at 10 mA is sufficient to give a noise immunity of 6.2 dB and an additional safety factor of about 1.8 dB can be obtained by running at slightly higher current. A larger amplitude optical signal also reduces the Single Event Upset (SEU) rate in the TTC system and an amplitude of 1 mW for the optical signal ensures that the resulting BER is always less than 10-9[9]. A fast rise and fall time is required for the VCSELs because the amplifier for the p-i-n diode receiver on the detector (DORIC4A) is AC coupled. The fast rise and fall times achievable with the VCSELs also helps to minimise the jitter of the recovered BC clock.
The manufacturer’s specifications for the VCSEL arrays are given in Table 3below.
Table 3 Specifications for the VCSEL arrays.
Characteristics / Min. / Typical / Max. / UnitsWavelength / 820 / ~840 / 860 / Nm
Output power coupled into 50m core SIMM fibre @ BPM DAC setting of 165 (equivalent to 10 mA). / 0.7 / 1.2 / - / mW
Threshold current / 3 / 6 / mA
Forward voltage @ 10mA / 2 / 2.5 / V
Reverse voltage / 2 / V
20%-80% Rise/Fall time / 1 / 2 / ns
Temperature range / 10 / 20 / 50 / °C (condition for package not chip)
3.3Array Packaging
The parts for the opto array sub-assembly are shown in Figure 2 below. An identical design is used for VCSEL and p-i-narray sub-assemblies, except for the opto array chip. The location of two precisely machined guide pinsdefines the alignment of fibres in an MT connector when the connector is inserted. The array chip is placed precisely on the base PCB with respect to the guide pins. The precise location between guide pins and opto array chip guarantees the alignment of the active elements of the opto array chip to the optical fibres. The opto array chips are wire bonded to the base PCB and the connection from the base PCB to the TX or RX PCBs is done via the lead frames as shown in Figure 2. The upper lead frame is used for the connections from the 12 individual anodes and the lower lead frame is used for the common cathode connections. A photograph of a VCSEL array mounted on a TX PCB is shown in Figure 3.
Figure 2 Schematic view of opto arraypackage assembly
Figure 3 Photograph of a VCSEL array mounted on a base PCB with the MT guide pins.
4.Off-Detector ASICs
4.1DRX-12
The DRX-12 ASIC is used to discriminate the electrical signals from the p-i-n arrays to reproduce the data signals from the SCT modules (see Figure 1). The ASIC contains 12 channels, each of which consists of a comparator with an LVDS output driver. The DRX-12 was fabricated in the AMS 0.8 m BiCMOS process using npn bipolar transistors[6]. The basic units for the design were copied from the DORIC4A[6]ASIC. The input comparators are DC coupled to allow for the NRZ data stream. Each channel of the DRX-12 has an individually adjustable threshold which can be set by an external reference voltage to correspond to an input signal amplitude in the range 0 to 255 A. The other change to the comparators compared to the DORIC4A is that there is no hysteresis, as this is not required for a DC coupled link.
4.2BPM-12
The BPM-12 ASIC is used to combine the 40 MHz BC clock and the 40 Mbits/s command data stream (see Figure 1). It consists of 12 channels of biphase mark encoding and VCSEL drive circuitry. Each channel has an input 40 Mbits/s data stream and there is also a common input 40 MHz system clock for all channels. The biphase mark encoding scheme is a DC balanced code which creates extra transitions to encode data “1”s as illustrated schematically in Figure 4 below. The latency between the input and output data must not be too long because of the fixed pipeline depth of the front-end electronics. The measured latency was 60 ns. The BPM-12 ASIC was also fabricated in the AMS 0.8 m BiCMOS process but used only CMOS transistors.
Figure 4Illustrationof the biphasemark Encoding Scheme. The top trace shows the input clock signal and the middle trace shows the input data. The bottom trace shows the resultingbiphase mark encoded data. The data “1” is encoded as an extra transition in the output.
4.2.1VCSEL Driver circuits
A very simple CMOS circuit is used to drive each VCSEL. A schematic diagram of one channel of the VCSEL driver circuit is shown in Figure 5 below. An external voltage (bias) drives current through a 2k resistor which is then amplified by two current mirrors each with a current gain of 4. The current to the VCSEL is switched on or off by a logical level which corresponds to the biphase mark encoded data for that channel.A small “bleed” current of around 1 mA is sent to the VCSEL during the off period in order to ensure a fast turn-on of the VCSEL. The current to the VCSEL for each channel is adjustable in the range 1 to 18 mA by means of an external voltage.
Figure 5 Schematic diagram of the VCSEL drive circuit.
4.2.2BPM-12 Adjustments
It is essential in the SCT pipelined system that the correct data for the event corresponding to a given L1 trigger is read out from the ABCD pipeline. This means that the L1 trigger must arrive at the ABCDs at the right time. This is achieved by setting the BPM-12 coarse delay register which delays the L1 signal by an integral number of clock cycles. This is performed by sending the data through flip flops clocked by the 40 MHz BC clock.
It is also necessary to adjust the delay of the 40 MHz BC clock so that the phase is correct with respect to the signals generated by particles crossing the detector module. A delay can be set for each BPM-12 channel by means of a 7 bit fine delay register which changes the delay in the range 0 to 35 ns (i.e. it covers the entire 25 ns period). This delay is generated by passing the signal through a selectable number of pairs of inverters.
In order to obtain an equal mark to space ratio (MSR) for the optical output, (this is necessary for the on-detector system to create a low jitter BC clock as discussed in Section 5.3.5) a MSR adjustment has been implemented which allows for the adjustment of the MSR of the BPM encoded data. The schematic diagram of the MSR adjustment is shown in Figure 6 below. The MSR of the signal is first reduced by connecting it to one input of an AND gate where the other input is a delayed version of the same signal. This signal is then fed to one input of an OR gate where the other input is a delayed version of the same signal. The delay for the second signal is adjustable by means of a register which controls how many pairs of inverters the signal is passed through. The effect of the OR gate is to stretch the width of the pulse so that the MSR is controlled by the length of this adjustable delay.
Figure 6 Schematic diagram of the mark to space ratio adjustment circuit in BPM-12.
4.3RX and TX Plug-in PCBs
Each RX PCB consists of a 12 channel p-i-n array with the precision mounted MT guide pins and a DRX-12 ASIC. The PCB also contains a multi-DAC[ix] for setting the thresholds for each channel. The RX PCB has a 40pin connector to allow it to be connected to the BOC card. Similarly each TX PCB consists of a 12 channel VCSEL array and a BPM-12 ASIC. The TX PCB also contains a multi-DACifor setting the voltages which control the VCSEL drive current.
5.Array and ASIC Performance
5.1p-i-nand p-i-n plus DRX-12 Measurements
5.1.1Analogue measurements
The rise and fall times of the bare p-i-n arrays were measured by feeding the signal from each channel of the array into a 50 resistor and displaying the voltage across the resistor on an oscilloscope. The rise and fall timesas a function of p-i-n bias voltage, for one channel of one array are shown in Figure 7below and the results from other channels on this array and other arrays were very similar.
Figure 7p-i-n20%-80% rise and fall times as a function of p-i-nbias.
Figure 7shows as expected that a fast response could be obtained for a p-i-nbias voltage of 5V. The p-i-nresponsivity was measured at a p-i-nbias of 5V and the resulting distribution of responsivities is shown in Figure 8 below. The distribution of the responsivities measured on the bare die array is very uniform, so the measured spread is probably due to the MT optical connector.