CS325 - Spring 2004

March 9, 2004

Homework Assignment 5

Due Wednesday 3/17/04 after class

A Problem for chapter 5 - Microprogramming:

This exercise is related to problem 5.27 in the text. In a previous assignment you had to write an assembly language program which copied a contiguous block of words from a given source to a given destination. You will now encapsulate this procedure into a single assembly language instruction called bcp (block copy). Since this instruction is somewhat complex to do in hardware, it will be implemented with a microprogram. Until now all MIPS instructions implemented in the multicycle nonpiplined design (ch. 5) had a maximum of 5 clock cycles. bcp, in contrast, will use an arbitrary number of cycles (microwords). By doing this exercise, you will gain a much deeper knowledge of the multicycles design in chapter 5 on which our pipelined design is based. You should review sections 5.4 and 5.5. The key items in these section which should be understood are: The multicycle datapath in fig 5.33 (p. 383), the 5 basic instruction steps given on pp. 385-389, the state diagram in fig 5.42 (p. 396), the microinstruction definition given in fig. C.21 (p. C-29) or fig 5.45 (p. 403), and the basic microprogram given in fig. 5.46 (p. 408). Figures C.20 and C.22 should also be useful.

The format of the bcp instruction will be: bcp rs, rd, rt, where rs contains the address of the first word of the source to be copied, rd contains the address of the first word of the destination block and rt contains the number of words to be copied. Although this has the format of a register word, there will be extensive memory activity in copying the data. You may assume that the bcp instruction has already been fetched and decoded by a microprogram similar to that in fig 5.46. Assume that the dispatch 1 table used in fig. 5.46 will branch to your microroutine when bcp is the opcode. All you have to do is write the microroutine for the bcp routine starting at the label of bcp.

The fact that the two source registers from the register file must be first buffered in the A and B registers causes extra cycles to be needed for this instruction. You may make the following extensions to the microinstruction definition as given in fig C.20: Assume the data path is modified such that, for this instruction, the register file registers could bypass the A and B registers and directly act as a source to the ALU. This means that you could modify the SRC1 and SRC2 fields of the micro word (see fig C.20) to contain the explicit register designator such as rs, rd, rt, or even a direct reference such as $4 or $t. In addition, assume that SRC1 and SRC2 may be extended to included small 5 bit constants such as 4 to be used for incrementing or decrementing. Also you may extend the Write ALU and Write MDR values of the Register control field to be Write ALU rg and Write MDR rg respectively, where rg is any register file designation (see fig C.20). Previously Write ALU and Write MDR always defaulted to whatever the corresponding registers rd and rt referred to as a destination. Now you could explicitly specify it as rg. Similarly you may extend the same field name (Write ALU) in the Memory field (see fig C.20) to Write ALU rg, where rg explicitly refers to any register in the register file rather than using only the B reg as a source of data to be written to memory.

Finally you may extend the sequencing field to do conditional branching within the microprogram. Let these new microprogram conditional branches be based on a test for zero on the ALUOut register. Use the following notation: if alu == 0 label and if alu != 0 label where label is any microprogram label.

Use the timing implied by the state diagram in fig. 5.42 as a model for the timing implied by your microprogram. Remember that in edge triggering methodology you can transfer the current contents of a state element through combinational logic to another state element in a single clock pulse (see fig. 5.2 and 5.3, pp. 342-343). You cannot transfer the new or potential state going into the first flip-flop, but only the current (old) state in this single clock pulse.

Write the microprogram in a tabular form in the style of fig 5.46. Explain each microinstruction with a comment at the end of each row in the table. If a field in a microinstruction is a don’t care or not asserted, put a dash in that field. I suggest that you lay out the table on a sheet in a horizontal or landscape orientation because the table is a bit wide with a normal orientation. Remember that going from the register file through the ALU and back to the register file or to memory takes a path through the ALUOut temporary register. Finally to make things consistent, if you need a temporary register, use $8 (same as $t0).

To get started your table could perhaps begin as follow:

LabelALUControlSRC1SRC2REGControlMemoryPCWritectlSequencingComments

BCPaddrt0---if alu==0 done move count to ALUOut & branh on 0

moveaddrs0---seqset ALUOut

with rs

... and so forth - good luck!

Write an overview of your design. Show modifications to the text book design by annotating or updating the data path (fig 5.33), the microword control bits (fig. C.21), the microprogrammed control unit as shown in fig. C.20, any additional dispatch tables for conditional branching (see fig C.22). Photocopy, scan, or use existing graphics from thee publishers website to make these updates. Freely use descriptive comments describing what you are doing.