A Comparison of Simulated and Measured Dynamic Power
Supply Current Profiles of VLSI Circuits
S. Thomas
ECE Department, University of North Carolina at Charlotte
9201 University City Blvd, Charlotte NC, 28223 USA
scthomas @ uncc.edu
ABSTRACT
This project presents a study based on simulations and measured data of circuits with built-in defects. By observing the dynamic power supply current of the circuits, an insight to the functionality of the devices can be gained. Comparisons of the simulations and the measurements show various levels of correlation between the two. Improved understanding of these matches and mismatches were utilized to better model the effect of defects on iDDT and improve future simulated fault models.
KEYWORDS
iDDT, Transient, Testing, Dynamic power supply, current, simulation, defects, fault models.
- INTRODUCTION
The dynamic power supply current, also known as iDDT, provides insight into the switching characteristics of a circuit and can be used to diagnose defects [1] - [3]. There are several different iDDT test techniques today, including different methods of interpreting the iDDT test data [4] - [12]. Unfortunately, it is very difficult to model the iDDT response of circuits. Simulations of the iDDT response are often inaccurate and there is a need to gather enough physical data that can be used to improve the accuracy of the fault models and subsequent simulations. This paper is an early study in the methods of correlating the simulations of defective circuits with the measured defective circuits.
Along with this deficiency of physical data is the overwhelming predominance of simulated data. Simulations of circuits are relatively fast and inexpensive to produce. Even older computer systems with processors that are considered outdated by today's standards can run software that creates acceptable circuit analysis results. Of course, the tradeoff of using these older systems is computational time. The ability to use readily available computer equipment to provide simulation data is an attractive option.
Another advantage of creating computer simulations is the ease and speed of repeating the experimental runs. Changing the location or the severity of a simulated defect can be as simple as modifying a single line of computer code. On the other hand, measured data from actual circuits requires a great deal more commitment. The designed circuits must be processed for fabrication. Of course the fabrication process will typically involve complex equipment and highly trained technicians. The entire process is expensive in terms of funds, time, and resources. Timely and cost-effective iterations of a circuit are not a luxury shared by both the fabrication and the simulation approach to research.
One disadvantage of simulated data is the question of reliability. Although measured data invariably contains some level of noise, the results can be considered true values that are as accurate as the technology allows. Simulated results raise into question the assumptions made by the software. Because an accurate voltage representation is as important as a true circuit description, many studies have focused on the simulation of the power supply [13] - [15]. Different methods to improve the accuracy of the simulations have included adding additional files to the circuit description, restricting simulations to particular operating conditions, and making voltage source impedance dynamic [16] - [18].
The previous research using the iDDT profiles of these types of small circuits concentrated on peak current values obtained from the circuits at the time of input transition [19]. This particular study focuses on the graphical results of the data. Therefore the data created and shown in these examples is very visual in nature. It involved a comparison of iDDT simulation data with iDDT measured data for simple circuit elements. Defects were inserted in different locations, and simulations were performed under the defective conditions. Then the circuits were fabricated and physical measurements were performed.
It is important to point out that large circuit effects were not taken into consideration at this stage of experimentation, and thus the results must be considered in this context. Also, the measured results have to be taken in light of experimentation set-up which is not completely noise free and includes but is by no means limited to probe inductance, Electromagnetic effects, and parasitics (capacitance, resistance, and inductance) from the padframe and the package. These unwanted parasitics were represented in the simulations using the typical values provided by the fabrication house and the measuring equipment manufacturer.
The defects inserted in the small test circuits included opens and shorts of various sizes to study their impact on iDDT. The test circuits were designed in a 0.5 um CMOS process and fabricated through MOSIS. The transistors were sized to be 5 x 2 for the NMOS and either 5 x 2 or 10 x 2 for the PMOS (depending on the circuit). Each test chip included one defect free copy of a circuit and several defective circuits. The method presented here uses an external resistor of 1K-Ohm connected between the chip supply pad and the power supply. The voltage drop across the resistor was measured as indicative of iDDT using Ohm's law. A 0.01F bypass capacitor was employed to reduce power supply noise. The IC was mounted on a custom manufactured PCB to ensure short leads and a stable ground plane to reduce ground bounce and minimize noise.
2. IDEAL VERSUS MEASURED
In order to assess the accuracy of iDDT simulation, one strategy is to start with an ideal simulation (without adding noise and parasitic effects) and comparing it against the measured data. Figure 1 shows an ideal sample input and its associated iDDT pulse created with simulation software. Figure 2 shows a measured iDDT pulse along with the input signal. Looking at the ideal simulation versus the actual signal, it is easy to see the similarities as well as the differences. Both signals rise from a LOW to a HIGH. However the measured signal shows both overshoot and a definite settling time as the signal settles to a steady state value. Also clearly seen on the measured trace and absent from the simulation is the noise riding on the signal.
Figure 1: Sample iDDT Simulated pulse. This figure shows the smooth signal and the absence of any noise.
These differences translate into the iDDT signals as well. Notice that the simulated iDDT pulse is lined up perfectly with the sample input signal. There appears to be no activity as long as the input is constant, regardless of the voltage level. In the measured signal the maximum value occurs in the later half of the input transition. Ringing is clearly visible on the measured iDDT trace. Although this type of noise can not be completely removed, its effects can be minimized. The basic rules for taking measurements with this type of laboratory equipment include good grounding practices, minimal wire lengths, and general isolation from noisy environments [20].
Figure 2: Measured iDDT pulse. This shows the actual measured results of an input and an iDDT signal. Both traces show the information as well as the presence of noise.
- THE EXPERIMENT
In this experiment, several test circuits were designed, simulated, fabricated, packaged in 40-pin DIP cases, and measured. A Tektronix TLA720 Tester was utilized for test generation and the output data was analyzed via a Tektronix TDS6604 Digital Storage Oscilloscope. This scope has the capability to measure signals at speeds of 6GHz and can take 20G Samples/sec. The computer simulation analysis of these fault models was performed with Mentor Graphics Eldo tool using ADK libraries and a Spice file circuit description.
Measurements were taken at both the rise and fall times of the input stimulus and compared to the simulated data. In some cases the measured data was found to be quite similar to those resulting from simulation. However in other cases the measurements did not seem to correlate very well with the computer predictions.
A typical example of this disagreement is evident in the measurements for the small adder shown in Figure 3. This adder circuit operates using negative logic for the outputs. However, the logic outputs in this case are immaterial since the investigation targets the iDDT current. Figure 3 shows the connections for the padframe power supply, the circuit power supply, as well as the inputs and the outputs for the circuit. It also indicates the input levels used to test the circuit. Notice that for this experiment only one input is allowed to change at a time.
Figure 3: The logic schematic for the adder circuit with negative logic, "Adder" on chip T24H-AR. Input A and Input B are also shown providing the inputs "00", "01", "11", "10", and returning to "00".
The simulated iDDT response of the adder circuit with negative logic is shown in Figure 4. This simulation does attempt to mimic reality by including the padframe, the package housing, and the measuring equipment. The resulting iDDT profile shows a medium-sized positive pulse as input A is raised, and a large negative swing as input B is raised. The simulated iDDT responses for the falling transitions of each of the inputs are predicted to be virtually negligible pulses.
Figure 4: Simulated waveforms for the negative logic circuit "Adder". The first transition causes a 6ns iDDT pulse with a magnitude of 96A. The second one is a 25ns pulse of 193A. The third and fourth are both 4ns disturbances of negative 42A to 35A respectively.
The measured iDDT response of this circuit is shown in Figure 5. Because of noise, the magnitudes of the pulses are not expected to give exact matches. However the visual profile of the iDDT currents do not appear to correlate very well. A large positive pulse is measured as input A is raised. However no significant pulse in either direction is detected as input B is raised. As input A is lowered in the simulation, the resulting iDDT is hardly noticeable. However when this pulse is measured using the oscilloscope, it gives a large negative pulse. Also adding to the confusion of this mismatch is the fact that lowering the inputs in the simulation gives a similar result, but gives differing results in reality.
The defect shown in Figure 6 is a severe open. It is located on the line controlling the gate of the PMOS transistor of an inverter. Both the NMOS and PMOS transistors have been equally sized to be 2 x 5 for this circuit. The buffer used in the circuit is also shown in this figure. As before, to mimic reality as closely as possible, the effects of the buffers were included in the computer simulation.
Figure 5: Measured data for the negative logic circuit “Adder”. The first and third transitions cause a pair of approximately 14.8ns iDDT disturbances of approximately 730 and -770A respectively. These pulses are opposite in direction. The second and fourth pulses cause smaller 11ns ripples of 250 to negative 250A.
Figure 6: The schematic for the defective inverter “def_inv9” on the chip T26B-CJ. This defect is an open gate on the PMOS transistor. The end result is that the output should be pulled low decisively, but should have some level of trouble being pulled high.
The simulated data for this defective inverter in Figure 7 shows some very interesting results. The iDDT pulses are dwarfed by a relatively large current of approximately 600A whenever the output of the inverter is being pulled low. The computer simulator seems to assume that the floating gate of the PMOS transistor is at or near zero charge. Therefore it is virtually grounded, or is close enough to ground potential to allow unwanted current to flow. This dramatic result is not seen in the measured data of Figure 8 shown below.
Figure 7: The simulated data for “def_inv9”. The PMOS transistor appears to be on, thus causing a DC current of 600A when the output of the inverter should be low.
Figure 8: The measured data for the “def_inv9” circuit. In the fabricated circuit, the floating gate of the PMOS transistor does not appear to be tied at (or near) ground potential. The measurement does appear to indicate that there is a slight DC offset, but the iDDT pulses are dominate with 360 and negative 380A lasting 6.8 and 9.6ns, respectively.
Although both of the previous examples provide simulated and measured iDDT data that seem to disagree, the results have been interpreted differently. The first example seemed to show random variations that can not be easily explained. The second example also provides mismatched profiles, but can be rationalized by observing the location of the defect and its effect on the iDDT signature. The circuit shown in Figure 9 provides an example of highly correlated data.
Figure 9: The schematic for the defective NOR gate “def_nor5” on chip T26B-BV. In this case, the defect is located on the gate of an NMOS transistor in the circuit.
Using the input pattern shown in Figure 9 for both the simulation and the measurement, the iDDT data profiles for the circuit were obtained. The simulated data is shown in Figure 10. The eight input switches give the following eight iDDT pulses:
-193A with a 30ns recovery,
11A for 2ns,
99A for 8ns,
37A for 4ns,
-174A with a 30ns recovery,
85A for 7ns,
a range of –28 to 39A for 5ns,
and 40A for 3ns.
Figure 10: The simulated data for the defective NOR circuit “def_nor5”. The eight input switches give eight distinct iDDT pulses.
The measured iDDT data shown in Figure 11 correlates very well with the simulation. The numbers for the pulses are as follows:
-315A with recovery and ringing,
203A for 10.4ns,
231A for 11.2ns,
-275A for 12ns,
-243A with recovery and ringing,
271A for 10.4ns,
184A for 12.8ns,
and -218A for 9.6ns.
Although the pulses do not perfectly agree in magnitude, the iDDT profiles of both the simulated and the measured do appear to be remarkably similar.
Figure 11: The Measured data for the defective “def_nor5” circuit.
Figure 12 shows a plot of the pulse magnitudes for both the simulated and measured iDDT data. This graphically shows that these visual traces provided in the previous figures can be mathematically quantified. Although a visual inspection undoubtedly does show agreement, the science does not have to rely on individual interpretation. Figure 13 shows an example of the opposite case by using the data from the adder circuit shown above. The data points shown clearly diverge.
Figure 12: The pulse magnitude plot for the highly correlated iDDT data from the defective “def_nor5”.
Figure 13: The pulse magnitude plot for the diverging iDDT data from the adder circuit with negative logic.
4. TEST CHIP DETAILS
This iDDT testing method uses a very simple and direct measurement method. Placing an external resistor on the power supply line and measuring the voltage gives the iDDT current using Ohm's Law. Ideally, this method can be used for any type of circuit. However in practice, some circuits are obviously more suited to this type of method.
In this case, the test circuits were fabricated with each circuit having its own power supply pin and ground pin. Figure 14 shows an example layout of the circuits under test. The setup shows Circuit 1 connected to a dedicated power supply through a resistor, R. Notice that each circuit has its own dedicated supply, a unique output, and a shared input. Note that buffers are used to drive the multiple circuits.
Figure 14: Example layout of a circuit used for iDDT testing. In this case Circuit 1 is configured for testing with an external resistor.
Each circuit can be individually tested, or directly compared to another circuit in real time since the inputs seen by each circuit is exactly the same. Very interesting data can be gathered when two different circuits are measured at the same time. For example, if a defect happened to cause a delay fault, it would be obvious in the measured data since they are all aligned with respect to time on the x-axis. Any critical timing jitter issues between circuit comparisons are eliminated in this manner. Similar layout strategies are used for the other test circuits.
CONCLUSION
Example studies of measured iDDT values compared to their simulated values from several circuits are presented above. The results of these studies have shown that ideal simulations do not always provide accurate predictions of the measured data for a variety of reasons. However, the measured iDDT profiles of these test circuits do meet various levels of correlation when matched with the computer simulations. Even though the measured iDDT peak magnitudes do differ from the simulated ones, it is encouraging to see the data follow some of the same trends as the simulations predict. Future work will include refining the fault models to more accurately represent the defects in the test circuits.
ACKNOWLEDGMENT
This work was partially funded by NSF and DARPA/NeoCAD.
REFERENCES
[1]R.Z. Makki, Shyang-Tai Su, and T. Nagle, "Transient power supply current testing of digital CMOS circuits," International Test Conference Proceedings, pp. 892–901, Oct. 1995.
[2]Doe Hyun Yoon, Hong Sik Kim, and Sungho Kang, "Dynamic power supply current test for CMOS SRAM," 6th International Conference on ICVC '99, pp. 399-402, Oct. 1999.