LAUREN D. MORIARTY
8760a Research Blvd #282
Austin Texas 78758
cell 512-632-3206
Texas Professional Engineer license 75025
EDUCATION
University of California, Berkeley, California.
B.S. Electrical Engineering and Computer Science, Dec.,1975
TOOL EXPERIENCE
Synopsys, Cadence, and Mentor simulation tools
Synopsys, Cadence, and Mentor synthesis tools.
Experience in Verilog and VHDL, Assertion based verification
Experience with Shell scripting, perl, C, TCL, C++, lisp.
Design entry (non HDL) with Apollo, Cadence,PCAD.
Familiar with ACAD and PCCARD tools
WORK EXPERIENCE
SUMMARY
20 years RTL design,verification and project engineering experience at Texas Instruments
as a Member of the Group Technical Staff, and 15 years of consulting including RTL design,
verification, and conducting Verilog and VHDL classes. In 2001, I started my own engineering
consulting company :Chaparral Design where I continue to work.
Feb 2001 to Present while at Chaparral Design LLC Senior Design Consultant
July 2010 to October 2013 A verification and production test support at NXP San Jose for communications chips With a ARM Cortex M3 or M4. Wrote C and C++ testcases, and created shell and perl scripts. Ported tests for use on testers for test and characterization. Modify and improve scripts and testbench verilog and vhdl code.
Dec 2007 to Dec 2008 A verification assignment at Qualcomm (RTP) on a
new ARM11 processor Design. Tests were assembly language and System Verilog
Assertions or testcases generated with perl scripts resulting in System Verilog SVA
files and commands for a Vera CPU model.
Dec 2006 to Dec 2007 A verification assignment at NXP in San Jose on both an
ARM9 based communications chip as well as an ARM7 based chip. The testbench
was verilog and the chip was vhdl. Test harness bfms were VHDL, Verilog and TCL.
I was responsible for running regression, debugging failures, writing tests in assembly
language and C, modifying the test bench for new features, and adding new testbench
logic and BFM’s .
Jan 2006 to Oct 2006 Boston Mass : Analog Devices. System level test
development and debug of communications chip with an embedded ARM7 and a
embedded AD2800 DSP processor. Ran regression, debugged failures, wrote assembly
tests for DSP and ARM core.
Nov 2005 to Jan 2006 Austin Texas : Sigmatel, Contract for verification of audio chip.
Ran test regressions, debugged failures, wrote new verilog tests. Test harness was in
perl and verilog.
July 2004 to Oct 2005 A second contract in Boston at Analog Devices. Activities
include writing system level tests using Verilog, Vhdl , Dsp (A.D.Blackfin) assembly
code , ARM assembly code, or C code. In addition have written some perl testbench
infrastructure scripts
Feb 2001 to Mar 2002 A Boston contract at Analog Devices as a member of a
verification team for a series of communications chips in Boston at Analog Devices.
Tasks included debugging RTL and gate level regression test failures by identifying the
logic or software cause. Wrote or modified existing Verilog or VHDL tests. Wrote Arm
assembly language tests. This simulation environment was ModelSim. The contract
lasted for 14 months.
Apr 2000 to Feb 2001
Qualis Design Austin, TX Senior Design Consultant
Participated in RTL verification assignments and taught courses in Verilog and VHDL. The
courses included basic VHDL or Verilog language as well as 5 day courses in Verilog (or
VHDL) for verification, Verilog (or VHDL) for synthesis, and Advanced Verilog (or VHDL).
The verification assignments included a two month assignment on a data formatting
section of a large ASIC at DataCube in Danvers Ma. and a 3 month on a very large
router ASIC at Nortel in Ottowa.
Aug 1996 to Apr 2000
Cadence Design Services Dallas, TX Senior Design Consultant
Joined Cadence in the Spectrum Design services group. Completed a number of design,
verification and training assignments. The design services group was dissolved in 1999.
-5 month Verilog design and verification assignment on a PCI audio Asic at Cirrus Logic.
-3 month silicon debug assignment at Cirrus when the chip went into production
-1 year design and verification assignment on a Mpeg 2 chip in Chicago
-8 month assignment as a member of a synthesis team on DSP chip at Texas
Instruments.
-6 month VHDL design and verification project on high speed processor. Test chip at Cray
Research in Chippewa Falls, WI. I was project lead designer.
-6 month assignment developing sections of SOC training.
-2 month project developing a verification plan for a Cache memory block at EVSX in Austin
-6 month assignment creating Verilog library models.
-In between assignments taught 5 day Verilog courses and one day Ambit synthesis course.
Jun 1995 to Aug 1996
Texas Instruments Dallas, TX System Engineer Advanced Microprocessor Group
Worked in a system engineering function. Task was to guarantee bus compatibility of
an X86 (P5) type processor. Developed verification plan and test procedures.
Oct. 1991 to Jun 1995
Texas Instruments Austin, TX Member of Group Technical Staff
Custom Manufacturing Design Services
Functioned as Program manager and Logic Designer for an Engineering service
organization. This group contracted to provide design and manufacturing services.
Designed a SPARC Motherboard used as the reference design by the T.I. SPARC group
in an application note. Modified design to fit different form factors. Provided schematics,
pwb layout, BOM, and 5 working prototypes. Designed 486 and 386 motherboards. Provided
Program Management for small manufacturing runs of numerous products. Purchased parts,
maintained inventory, supervised build, test, and ship of product.
Principle engineer on design of PCI bus interface chip for a T.I. Token Ring chip. I was
responsible for the design, verification and the synthesis. Lead 3 engineers and 2 co-ops.
1990 to 1991
Texas Instruments Houston, TX Member of Group Technical Staff SPARC Applications
One year assignment on loan to Semiconductor Group to provide systems experience in
SPARC Applications for the TMS390S50 Risc processor. Wrote data sheets, application notes,
and interfaced with customers. Conducted training for product engineers and test engineers.
1983 to 1990
Texas Instruments Austin, TX Member of Group Technical Staff
Advanced Hardware Development
Participated in numerous circuit board logic designs and ASIC designs as either project engineer,
lead engineer, or as member of design team. Worked with junior as lead and mentor on the
design a number of PWB projects.
Participated in the design of Explorer (LISP) System checkout hardware and was responsible for
integration of hardware and Lisp software used in that station. Project Engineer on Micro-Channel
Co-processor add-in board. Design team consisted of 4 engineers and 2 technicians. Consulted with
semiconductor group in definition and design of NuBus chip set. Designed and simulated control part
(74ACT2440). Specified data path part (74ACT2420) and oversaw technical aspects of the project.
Co-authored application notes and presented at working sessions at Buscon East and Buscon West.
Participated as member of technical team studying the feasibility of building an emulator for an Array
Super Computer. Principle design Engineer on a 68020 communications board. Designed board logic
and as well as large ASIC. In addition to the above assignments was the Electrical Engineering
representative on the DSG Design Review Team.
1977 to 1983
Texas Instruments Austin, Tx Senior Design Engineer Hardware development
Principle designer on numerous PWBs including Cache, memory arrays, disk controller and buscoupler. Project Engineer for a number of projects with design teams up to 3 engineers and 2 technicians. In addition to logic design acquired reputation as bus expert and trouble shooter. Consulted with and assisted Field Service and Sustaining Engineering in solving numerous bus and system related
problems. Selected as Member of the Group Technical Staff in 1983.
1975 to 1977
Texas Instruments Austin, TX Design Engineer
Test Engineering and designed stand-alone test equipment.
1971 to 1975
Searle CPSI Emeryville, CA Senior Technician
1969 to 1971
AT&T Oakland, CA Technician
1965 to 1969
USAF Electronics Technician Instructor
1963 to 1965
AT&T Oakland, CA Technician
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