KONIX MULTI SYSTEM (C) 1988, 1989 Flare Technology Ltd

Hardware Reference Guide Page 18

THE KONIX MULTI SYSTEM

8086 BASED PRODUCTION VERSION

HARDWARE REFERENCE GUIDE

Version 1.06

by Martin Brennan, Ben Cheese and John Mathieson,

Flare Technology Limited

Unit O

The Paddocks Trading Estate

347 Cherry Hinton Road

Cambridge

CB1 4DH

DISCLAIMER AND WARNINGS

Neither the whole nor any part of the information contained herein, nor any product described in this manual may be adapted or reproduced in any form except with the prior approval of Flare Technology Limited (‘Flare’) and Creative Devices Research Limited (‘CDRL’).

All information of a technical nature and particulars of the product are given by Flare in good faith. However, it is acknowledged that there may be errors or omissions in this manual.

Flare and CDRL have a policy of continuous review and improvement of their designs, therefore information in this manual is subject to change without notice.

Whilst every effort will be made to remain compatible with existing standards, software authors and add-on hardware designers should note that:

1 - Use of undocumented features or modes

2 - Use of I/O or Memory locations marked as `reserved'

3 - Assumptions about values read from undocumented register bits

4 - Setting of unused register bits to other than 0

5 - Use of the hardware in a manner not indicated in this or other Flare documentation to be valid are all actions that are liable to make their software or hardware products not compatible with future revisions of the Konix Multi System.

TABLE OF CONTENTS

DISCLAIMER AND WARNINGS 2

TABLE OF CONTENTS 3

THE KONIX MULTI SYSTEM 6

1. INTRODUCTION 6

1.1. This Document 6

2. ARCHITECTURE 6

2.1. Memory Map 8

2.2. I/O Map 9

2.3. Memory Interface Timing 10

2.4. Video Cycles 10

2.5. 8086 CPU cycles 10

THE VIDEO CONTROLLER 12

1. INTRODUCTION 12

2. THE SCREEN MAP AND DISPLAY MODES 12

2.1. Low resolution 200 line display 13

2.2. Medium resolution 200 line display 13

2.3. High resolution 200 line display 13

2.4. Logical to Physical Colour Translation 14

2.5. Colour Hold Mode 14

2.6. Variable Resolution Mode 14

2.7. Border Colour 15

3. SCREEN TIMING 15

3.1. Video Line Timing 15

3.2. Video Field Timing 15

4. THE REGISTERS 16

4.1. Interrupt register 16

4.2. Start register 16

4.3. Horizontal count register 16

4.4. Vertical count register 17

4.5. Scroll registers 17

4.6. Screen mode register 17

4.7. Border colour register 17

4.8. Colour mask and palette index 18

4.9. End register 18

4.10. Memory configuration 18

4.11. General Purpose register 18

4.12. Diagnostic 19

4.13. Interrupt disable register 19

4.14. Joystick output register 19

4.15. Light-pen registers 19

4.16. Joystick input register 19

4.17. Status register 20

5. OPERATION OF THE CONTROLLER 21

5.1. Refresh mechanism 21

5.2. Interrupt mechanism 21

5.3. A/D Comparators 21

5.4. Peripheral I/O 21

THE DIGITAL SOUND PROCESSOR 22

1. INTRODUCTION 22

2. ARCHITECTURE 22

2.1. ALU 23

2.2. Multiplier 24

2.3. DMA Channel 24

3. MEMORY 25

4. DSP INSTRUCTION SET 27

4.1. Conditional Instructions 27

4.2. Indexed Addressing 27

4.3. Opcodes 27

5. HOST MEMORY MAP 29

6. DATA TRANSFER BETWEEN HOST AND DSP 30

6.1. Under DSP control - DMA transfer 30

6.2. Under Host Control - INTRUDE 32

7. ILLEGAL INSTRUCTION COMBINATIONS 33

7.1. Multiply / Multiply-Accumulate operations 33

7.2. DAC instructions 33

THE BLITTER 34

1. INTRODUCTION 34

1.1. This Section 34

1.2. The Blitter 34

2. ARCHITECTURE 34

2.1. Overview 34

2.2. The Data Path 35

2.3. The Address Generator 38

2.4. The Sequencer 39

2.5. Memory Interface and Interrupts 45

3. MODES OF OPERATION 46

3.1. Simple Memory Fill and Copy Operations 46

3.2. Line Drawing 47

3.3. Example Program 49

3.4. Character Painting 50

4. BLITTER COMMAND FORMAT 52

4.1. Command and Mode Control Bits 53

4.2. Step Register and Enhanced Step Control Bits 54

4.3. Comparator Control Bits 54

4.4. Logic Function Unit Control Bits 54

4.5. Source Address Register and Control Bits 55

4.6. Destination Address Register and Control Bits 55

4.7. Program Address Register 55

5. BLITTER I/O REGISTERS 56

5.1. Destination Register 0 56

5.2. Destination Register 1 56

5.3. Source Register 0 56

5.4. Source Register 1 57

5.5. Blitter Program Address 57

5.6. Blitter Command Register 57

5.7. Blitter Control Register 58

THE DISK CONTROLLER 59

1. INTRODUCTION 59

1.1. Disk Format 59

1.2. Read Operation 59

1.3. DMA Interface 60

1.4. Block Diagram 60

1.5. Write Operation 60

2. REGISTERS 61

2.1. Floppy Disk Control Register 61

2.2. Disk Status Port 62

2.3. Drive Control Register 63

2.4. Drive Status Port 63

3. ERROR HANDLING AND DATA INTEGRITY 64

APPENDICES 65

A. The DSP Arithmetic Logic Unit 65

B. The DSP Assembler Manual 66

1. How to invoke the assembler 66

2. Source File format 66

3. Error Reporting 71

THE KONIX MULTI SYSTEM

1. INTRODUCTION

The Konix Multi System is designed to be an ultra-high performance arcade games engine. It achieves this by utilising three processors, one general purpose processor, an Intel 8086, and two highly specialised co-processors, the Blitter and the DSP.

The system is intended to be as simple as possible, while still providing the necessary performance levels (compare the complexity of the Amiga); and to provide as much flexibility as the programmer may wish.

1.1 This Document

This document is intended to be a useful guide to the assembly language programmer who wishes to drive the hardware facilities provided in an effective manner. It is not for novices.

This first section discusses the computer system as a whole, and is followed by individual sections discussing each sub-module. The best approach is to read it through first, then to approach it as a reference guide once the overall context of sections is understood.

2. ARCHITECTURE

The Konix Multi System computer electronics are largely contained within one massive custom logic chip, known as an ASIC (for Application Specific Integrated Circuit). The system memory and 8086 CPU lie outside the ASIC. This diagram summarises the architecture:

Video

┌─────────────║─────┐

┌────────────┐ │ ┌───────────╨─┐ │ ┌──────────┐

│8086 CPU ╞══════╡Video/Memory ╞═══════════╡Screen │

│6 MHz │ │ │Controller │ ║ │ ║ │RAM │

└────────────┘ │ └─────────────┘ ║ │ ║ └──────────┘

│ ┌─────────────┐ ║ │ ║

│ │Floppy Disk ╞═╣ │ ║ ┌──────────┐

│ │Read DMA │ ║ │ ╠════╡System │

│ └─────────────┘ ║ │ ║ │RAM │

│ ┌─────────────┐ ║ │ ║ └──────────┘

│ │Blitter ╞═╣ │ ║

│ │Co-processor │ ║ │ ║ ┌──────────┐

│ └─────────────┘ ║ │ ╚════╡Bootstrap │

│ ┌─────────────┐ ║ │ │ROM │

│ │DSP ╞═╝ │ └──────────┘

│ │Processor ╞═══════╗

│ └──╥────────╥─┘ │ Audio

│ ┌──╨────────╨─┐ │

│ │DSP 32-bit │ │

│ │ROM and RAM │ │

│ └─────────────┘ │

│ASIC │

└───────────────────┘

Sharing the main memory bus are four bus masters; the DSP, the Floppy Disk Interface, the Blitter and the 8086. Only one of the bus masters may own the bus at any one time, and a priority for the bus exists, giving the DSP highest priority, followed by the Floppy Disk Controller, the Blitter and the CPU, in descending order.

The video controller controls the bus, and provides the memory timing signals for memory devices attached to the bus. It also requires memory cycles, and has effectively the highest priority on the bus. It will suspend bus master operations during video lines for brief periods to fetch video display data, and to refresh dynamic RAM. It interfaces with the 8086 CPU, and performs the bus de-multiplexing for it.

The DSP is a simple, very high-speed processor for sound synthesis; operating at 12 MIPs. It has access to the main bus via a DMA controller which allows it to read and write bytes or words from main memory. These transfers occur in short bursts, and are under DSP program control. The DSP actually executes programs and stores data in its own private high speed memory.

The Floppy Disk Read DMA channel allows the system to transfer floppy disk read data into main memory without any software overhead.

The Blitter is a graphics processor for fast screen updates and animation, acting as a hardware graphics sub-routine for the 8086. It will become bus master throughout a Blitter program operation, and may therefore own the bus for considerable periods.

However, its priority over the CPU is not total, as it may be requested to give up the bus to the CPU when an interrupt occurs.

The 8086 CPU is the lowest priority bus master at the system level, but has complete control of the other two processors, and so the use of the bus is entirely under program control.

2.1 Memory Map

Two memory maps are supported by the system. Selection of them is described below in the Video Controller section.

Map 0 Map 1

FFFFF ┌──────────────────┐ ┌──────────────────┐

│ │ │ │

│ 16-bit │ │ 16-bit │

│ ROM │ │ ROM │

│ │ │ │

C2000 ├──────────────────┤ ├──────────────────┤

│reserved │ │reserved │

C1600 ├──────────────────┤ ├──────────────────┤

│DSP Program RAM │ │DSP Program RAM │

C1400 ├──────────────────┤ ├──────────────────┤

│DSP Data RAM │ │DSP Data RAM │

C1300 ├──────────────────┤ ├──────────────────┤

│DSP Registers │ │DSP Registers │

C1280 ├──────────────────┤ ├──────────────────┤

│DSP Data Constants│ │DSP Data Constants│

C1200 ├──────────────────┤ ├──────────────────┤

│DSP Data ROM │ │DSP Data ROM │

C1000 ├──────────────────┤ ├──────────────────┤

│reserved │ │reserved │

C0200 ├──────────────────┤ ├──────────────────┤

│Palette RAM │ │Palette RAM │

C0000 ├──────────────────┤ ├──────────────────┤

│ │ │ │

│ 16-bit │ │ 16-bit │

│ Screen RAM │ │ System RAM │

│ │ │ │

80000 ├──────────────────┤ │ │

│ │ │ │

│ 16-bit │ │ │

│ System RAM │ │ │

│ │ │ │

40000 │ │ ├──────────────────┤

│ │ │ │

│ │ │ 16-bit │

│ │ │ Screen RAM │

│ │ │ │

00000 └──────────────────┘ └──────────────────┘

Map one is the most useful arrangement for the standard machine as it provides RAM at 00000 for the vectors. In it the one Megabyte memory space is divided into four logical areas, with the 256K area based at 00000h allocated for internal 16-bit screen RAM, the 512K area based at 40000h for expansion RAM, the 8K byte area of memory based at C0000h is the internal memory of the ASIC, and the 248K area based C2000h is ROM.

2.2 I/O Map

Address Write Register Read Register

00 Interrupt line Horizontal light-pen

02 - Vertical light-pen

04 Screen start -

08 Horizontal counter Joystick inputs

0C Vertical counter Machine status

10 Scroll register 1 -

12 Scroll register 2 -

14 Scroll register 3 -

16 Interrupt acknowledge -

18 Screen mode -

1A Border colour -

1E Colour mask -

20 Palette index -

22 Screen end -

26 Memory configuration -

28 General purpose -

2A Diagnostic -

2C Interrupt disable -

2E Joystick outputs -

40 Blitter program address Blitter destination address 0

42 Blitter command Blitter destination address 1

44 Blitter control Blitter source address 0

46 - Blitter source address 1

48 Floppy read control Floppy read status

80 Drive control Drive status

88-8F General purpose I/O decode 1

90-97 General purpose I/O decode 2

98-9F General purpose I/O decode 3

A0-FF Free for third party peripheral I/O

The 8086 I/O space is internally decoded to eight bits, as shown above. I/O locations above A0h are free for third party I/O expansion. In addition to this, three spare general purpose I/O decodes are provided - these may be used to provide an active low chip enables to external devices, note that RD and WR should also be connected to the devices.

All internal I/O locations are on even boundaries, and word wide I/O reads and write may be performed where appropriate. Do not perform byte wide I/O writes on word-wide write registers, and do not perform any I/O cycles to odd addresses.

All locations marked with a dash “-” are reserved for future expansion or

manufacturing test modes. Do not write to any of these locations or use them for external I/O.

Analogue Inputs

In addition to switch controls, the machine has three potentiometer based analogue controls, and a light-pen type input.

The potentiometer output voltages are measured by comparing them to a voltage ramp which is reset every vertical video synchronization pulse. When the potentiometer voltage equals the ramp voltage an interrupt is generated, one interrupt being generated in every video frame for each of the analogue inputs.

When one of these interrupts occurs, the CPU may read the video vertical counter, #and from this estimate the analogue voltage being measured. The interrupt mechanism is described in greater detail in the Video Controller section below.

When a second machine is connected in slave mode, its potentiometer values may also be read, as an analogue multiplexer selects between the internal potentiometers, and a second set connected to the joystick port. In this mode, the two sets of potentiometers would be read on alternate video fields. It is also possible that other analogue controls might be attached to the joystick port, and these would be read in a similar manner. The analogue multiplexer control line is in the General Purpose register.

A light-pen, or other beam detecting device such as a gun, may also be connected.

This function is part of the Video Controller described below.

Memory Interface Timing

All memory timing is based on a single master clock rate, which is either four times the European PAL TV standard chroma carrier frequency, or five times the American NTSC TV standard chroma carrier frequency. These give master clock rates of:

NTSC 17.897725 MHz

PAL 17.734475 MHz

This clock rate is divided by 1.5 to produce the co-processor and memory interface clock, nominally 12 MHz. This is further divided by 2 to give the processor clock, nominally 6 MHz.

In the descriptions below timings either apply to both systems, or two numbers are given, the second one in brackets being the NTSC system figure.

Video Cycles

The memory interface is available to the current bus master throughout it’s ownership, except during video cycles. When video data is being fetched or dynamic RAM is being refreshed, wait states may be inserted into co-processor memory cycles. This mechanism does not affect the CPU. Video lines are nominally 64(63.5) micro-seconds, and 44 of these are used for video or refresh. This mechanism is described in greater detail in the Video Controller section.

8086 CPU cycles

All CPU memory cycles take place in four processor clock ticks, with no wait states inserted, in all the types of memory available (this gives a memory cycle time of 670 ns or about 1.5 MHz). However, Refresh the video controller requires that all CPU cycles occur on a 4 T-state boundary, and may insert wait states to align the processor cycle onto a four T-state boundary, i.e. up to three wait cycles may occur.

This alignment operation, once it has occurred, will not cause any further wait states as long as the processor continues to request memory cycles every four T-states.

Should its bus interface pause, then it will have to pause for a multiple of 4 T-states.