Aldec Active HDL (Verilog) 6.1 Tutorial
EGR 240
Create a subdirectory EGR240\Lab5 on the Desktop.
Start the program by double-clicking the Active-HDL 6.1 icon on the desktop.
Select VERILOG Design Entry and click Next.
Select Create new workspace and click OK.
Browse to your directory, type gates for the workspace name and click OK.
Select Create an empty design and click Next.
Just click Next
Type gatesA for the design name and click Next.
Click Finish.
Click on HDE.
Select Verilog
and Click OK.
Click Next.
Type gates2
and click Next.
Click New. Type A.
Click New.
Type B.
Click New.
Type Z.
Click Out.
Set Array Indexes
to 1:6.
Click Finish.
This will generate a Verilog template with the input and output signals filled in. Delete all generated code above the module statement.
Click Save
Click on
Structure
Click on the waveform icon.
Select gates2
Click on gates2
and
drag it to here.
Grab B and move
it up to 2nd place
Select Simulation -> Initialize Simulation
Make sure signal names are in the order: A, B, Z.
Right-click on A and select Stimulators.
Select Clock and set Frequency to 25 MHz
Click Apply
Click on B, select Clock and set Frequency to 50 MHz
Click Apply
Click Close
Set simulation time to 200 ns
Click here to run simulation
Click + sign to show all elements of Z.
Print out the waveform by selecting File -> Print from the menu bar.
Select Design -> Add Files to Design… and add the file gates4.v to the design.
Make sure you click “Make a local copy” when adding gates4.v.
Right-click and compile gates4.v.
Click on Structure
Click on the waveform icon.
Select gates4
Click on gates4
and
drag it to here.
Select Simulation -> Initialize Simulation
If necessary rearrange the order of signals to: X, Z, Y
Right-click on X and set stimulator to Counter. Set Binary – Hexadecimal – 20 ns
Click Apply
Click Close
Set simulation time to 400 ns
Click here to run simulation
Use magnifying glasses to zoom
in and out
Click + signs to expand Z and Y outputs.
Print out the waveform by selecting File -> Print from the menu bar.
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