ECE 232: Homework # 7
Due 5/1/2010
1. [15 pts] Consider a virtual memory system with the following properties: (i) 36 bit virtual address; (ii) 16KB pages; (iii) 32-bit physical byte address. What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty and use bits take a total of 5 bits and all the virtual pages are in use, i.e., disk addresses are not stored in the page table.
2. [15 pts] A processor has 16-entry TLB and uses 4KB pages. What are the performance consequences of this memory system (i.e., what is the TLB hit rate) if a program accesses a 2MB section of memory where all valid addresses are equally likely in each consecutive memory access. If the number of entries in TLB cannot be increased, what can you do to increase the performance?
3. [25 pts] Compare two designs of a computing system: (i) 1KB L1 cache with miss-rate of 11% and hit-time of 0.62ns; (ii) 2KB cache with miss-rate of 8% and hit-time of 0.66ns. For both the main memory access takes 80ns and 32% of the executed instructions access data in memory.
a. Why is the hit-time of design (ii) higher than that of design (i)?
b. Assuming that the L1 hit-time determines the processor cycle time, what are the clock frequencies of the two designs?
c. Calculate the Average Memory Access Time (AMAT) for the two designs.
d. Assuming a base CPI of 1.6, what is the total CPI for each design? Which would be faster?
4. [25 pts] A virtual memory system has 4KB pages, a 4-entry fully associative TLB and uses LRU replacement. The following stream of virtual addresses is generated by the processor: 4095, 31272, 15789, 15000, 4096, 8190. The next two tables show the initial contents of the TLB and the page table. Assume that the recent usage of the 4 TLB entries was in their order, i.e., entry 0 was the most recently used while entry 3 was the least recently used.
No. / Valid / Tag / PPN0 / 1 / 11 / 12
1 / 1 / 7 / 4
2 / 1 / 3 / 6
3 / 1 / 4 / 9
Entry No. / 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11
Valid / 1 / 0 / 0 / 1 / 1 / 1 / 0 / 1 / 0 / 0 / 1 / 1
PPN or disk / 5 / disk / disk / 6 / 9 / 11 / disk / 4 / disk / disk / 3 / 12
a. For the given stream of addresses show the final state of the TLB and page table and for each reference indicate if it is a TLB hit, a page table hit or a page fault.
b. Repeat (a) if the TLB is a 2-way set associative (the current 1st two rows now constitute a single set) with the following initial contents and the right entry being the least recently used.
Set No. / Valid / Tag / PPN / Valid / Tag / PPN0 / 1 / 2 / 9 / 1 / 4 / 9
1 / 1 / 3 / 6 / 1 / 7 / 4
5. [20 pts] A disk has 9ms average seek time, rotates at 7200 RPM, has a data transfer rate of 30 Mbytes/sec and 0.1ms controller overhead. Calculate the average time to read a 1024-byte sector from the disk. Calculate the minimum time to read a 1024-byte sector from the disk.