VIKAS KAPUR
981 Wisteria Terrace E-mail:
Sunnyvale, CA 94086 Cell: (408) 373-3499
Passport status: US citizen/passport holder Hm: (408) 736-8027
OBJECTIVE
A product position in high-technology enterprise firms that fully leverages and challenges my extended EDA
technology and consulting experience and background.
SUMMARY
Presently hold over thirteen years direct industry experience focused most strongly on IC Solutions Business Unit
and Systems+Solutions Business Units at Cadence Design Systems.
· Developed and and supported industry strength design automation flows and software for several years and have extensive experience in marketing, design and consulting with end-user engineering clients in the chip and system design community on designs and flows, implementations, processes and specifications. Expertise in EDA flows including First Encounter, NanoRoute clocktree generation, delay calculation, signal integrity, timing analysis
· Simultaneously led cross-functional teams and worked with senior management at the VP and Group Director level for project management and marketing, sales analysis, tool licensing, market planning and implementation. Presently maintain many long-time contacts in the chip design community across enterprise accounts as well as startup organizations on a local and national basis.
· Presently hold an MBA from UC Berkeley (obtained while working full-time) with a focus on emerging technology markets, competitive and corporate strategies and analysis in high technology based on solutions drawn from financial, marketing and operational initiatives.
EXPERIENCE
1. Cadence Design Systems, Member Consulting Staff and Project Lead 1992-present
System Design & Functional Verification Business Unit
· Lead Flow validation for next-generation Hardware-Software Co-Design (NCSim-SystemC/VCC/Testbuilder)
design framework for System-on-Chip (SOC) strategy working with developers, operations, sales and end-user
engineering clients including Methodology Services on embedded software and wireless design. Extensive
knowledge in front-end system design and architectural/behavioral models utilizing C, Verilog and System-C.
· Drive worldwide team of five system design engineers as project lead focusing on marketing solutions and
launch deliveries. Representative projects include multiple releases commencing from early Alpha to the
current Version 2.2 initiative and the ongoing Intellectual Property modeling project.
· NCSim-SystemC/VCC is a key player in the ESDA (Electronic System Design Automation) space covering
wireless, automotive and interactive Internet electronic design with projected customer revenues in the $50B
range by FY2005.
Deep Sub-Micron IC Solutions Business Unit
· Key Contributor in developing advanced Placement Based Synthesis (PBS) initiative for IC Design (focused on noise and timing optimization based on placement delay vs. fanout loading)
· PBS marketing and business development position involved extensive interfacing with end-user engineering clients such as NEC, Toshiba, Sun, TI and in-house Methodology Services group. Market penetration and customization for individual clients, tool acceptance criteria and benchmarks, tool propagation role with clients and technical evangelizing and selling of the methodology and related tools to first-time users
· Product development position involved individual design, specification, implementation and roll-out of
six major releases of the PBS suite of products. Recognized with Special Achievement award for successfully meeting and exceeding key customer requirements in PBS tool performance. Strong background in physical and geometric databases and algorithms for noise and timing analysis and library management. Extensive experience in back-end design comprising signal integrity, noise, place and route and clocktree and physical synthesis.
PBS played a key role in the current SOC Encounter and PKS strategy and was one of the fastest revenue generators
in the Place&Route, Synthesis&Timing division in the IC Business Unit
(contd: Vikas Kapur)
2. Mentor Graphics, CAD Applications Design 1990-1992
· Automated test pattern generation (ATPG) methodology marketing/sales for Functional Verification initiatives.
· Direct application consulting for ATPG to 10-15 person CAD groups at Sun and Texas Instruments, respectively.
· Development of methodologies for in-house design flows across Mentor Graphics tool suites.
SKILLS
· Computer Languages: C++, Perl, Tcl/tk, Unix shell programming, core Java programming, HTML and CGI
· EDA Tools: First Encounter SE-PKS, Nanoroute, NC-Sim Verilog, SystemC, SPW, Testbuilder, AMS, SPICE
· Operating Systems and Platforms: UNIX, Linux, Windows 2K, SUN Solaris 2.x, Microsoft Office
· Home LAN: Developed and currently maintain a broadband home office solution comprising a high-end
networked personal computer and a SUN IPX SparcStation with high-speed Internet connectivity for 24/7 access
EDUCATION
Master of Business Administration (MBA) 9/96 - 5/99
Haas School of Business, University of California, Berkeley
· Overall emphasis in corporate and competitive strategy in high technologies leveraging financial, marketing and operational solutions.
· Over 200+ case studies in 18 core courses with additional 12 group projects comprising 4-5 cross-functional
team members. Team projects included:
· Financial competitive analysis for Cadence Design Systems presented to SVP; Synthesis, Place&Route Group.
· Organizational strategy for Place/Route, Synthesis/Timing Division at Cadence presented to division VP
· Digital certification case study for VeriSign corporation focused on market alliance strategies.
· Risk management strategy for leveraged options presented to Quantal Financial.
Master of Science, Computer Engineering (MSEE)
Department of Electrical and Computer Engineering, University of California, Santa Barbara
· Broad EECS course-work in Electronic Design Automation, ASIC/VLSI Design and SOC design, Computer Architecture, Computer Networks and Distributed Computer Communication Systems.
· Regents Tuition Fellowship award; published in ACM Sigmetrics conference on the mathematical modeling of Distributed Networks using Coupon collecting algorithms.
Bachelor of Technology, Electrical Engineering
Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India
· Bachelor Thesis: “Design of Graphic/Alphanumeric Video Controller Adapter utilizing Motorola 680X0
processor environment”
· Government of India National Science Award 1984-1988
ADDITIONAL INFORMATION/INTERESTS
· NAUI certified scuba diver, FAA licensed private pilot over eighteen years, longtime backpacker and cross-country/downhill skier in Sierra Nevadas, varsity basketball and swim teams, Red-Cross licensed swim instructor
· Languages: Very fluent in English – longtime German speaker (certification with Goethe Institute, Munich)
· Volunteer interests as California certified EMT at local children hospitals since 1992; Child Advocate volunteer with Santa Clara County Juvenile Court since 1994; IEEE-SIGDA Minority Student Counselor since 1994.
· Longtime international traveler: lived four years in Eritrea, Africa; extensive travel in the US and Europe
· Other interests: world affairs, mathematical puzzles, presentation and multimedia for business.
· US citizen/passport holder.