8818, Brae Bend, San Antonio, TX78249; (210)-410-7371;

Chirag Parikh

8818, Brae Bend, San Antonio, TX78249; (210)-410-7371;

OBJECTIVE

Seeking a challenging position in the Digital field to fully leverage gained experience and acquired software and hardware skills effectively.

EDUCATION

University of Texas at San Antonio

Doctor of Philosophy in Electrical Engineering(concentration: Digital),In progress

Cumulative GPA = 3.91 / 4.0, Major GPA = 3.91 / 4.0

Masters of Science in Electrical Engineering(concentration: Digital),2003

Cumulative GPA = 3.74 / 4.0, Major GPA = 3.90 / 4.0

Fr. Conceicao Rodrigues College of Engineering

Bachelor of Engineering in Computer Engineering, 2000

TECHNICAL SKILLS

Languages: C/C++, Pascal, Assembly language (Intel: 8085,8086 Motorola: 68HC12, 9S12),

Verilog HDL

Software:MATLAB, PSPICE, MAGIC,SPICE, Visual Basic, XILINX FPGA Navigator, Modelsim Simulator, Mentor Graphics, Embedded Development Kit, Code Composer Studio, CodeWarrior, Mini IDE, LogicAid, SimuAid

PROFESSIONAL EXPERIENCE

Intern, DELL Products, Server Test Department, TX 2003

• Developed test cases and designed report for the group
• Studied the current code development process, identified flaws and recommended improvements

Programmer, L&T Information Technology Limited, Powai, India 2000

• Developed software for managing certain processes in training program life cycle

• Developed using Visual Basic as front end and MS Access as back end

DOCTORAL THESIS (In Progress)

Power Analysis and Optimization of 802.11i Security Protocol for PDA type devices

Develop 802.11i security protocol involving AES encryption algorithm and 802.1x Authentication protocol involving EAP-TTLS mechanism for wireless networks. Analyze the power consumed by the design using Xilinx XPower Tool as the implemented protocol was targeted at PDA-type devices. Develop the protocol for different platforms and analyze the speed and power consumption on those platforms.

MASTER THESIS

Performance Evaluation of Cryptographic Algorithms

Implemented (DES, Triple-DES and IDEA) cryptographic algorithms that are widely used for bulk data and link encryption. Evaluated the suitability of aforementioned algorithms for FPGA-based implementations and also compared the results with other existing implementations. The design was coded in Verilog HDL, synthesized using Xilinx Synthesis Tool and implemented in Xilinx FPGA (Virtex/Virtex-2) devices. Algorithms were designed in full duplex and resource efficient modes according to the usage.

RESEARCH EXPERIENCE

Developed embedded cryptographic cores, capable of performing encryption/decryption on incoming packet using various cryptographic algorithms like DES, Triple-DES, AES and IDEA.Key generation was done in software and cryptographic core was developed in hardware. Core was developed using Xilinx FPGA, modeled using Verilog HDL and C and verified using Modeltech’s ModelSim Simulator.

Chirag Parikh

8818, Brae Bend, San Antonio, TX78249; (210)-410-7371;

TEACHING EXPERIENCE

Teaching Assistant in Electrical Engineering department at UTSA 2000 – 2002, 2004 – 2007

Conducted labs, problem-solving classes, quizzes and exams for:

• Logic Design, Computer Organization, Microprocessor systems and Applied Engineering Analysis
• Advanced Engineering Labs, FPGA/Verilog and Hardware Implementation of DSP algorithms

COURSES / PROJECTS

• Design and implemented an embedded application to detect and eliminate various scenarios of SYN Flooding in wired network (Embedded Systems - 2005)
• Designed and compared different types of signed and unsigned dividers and multipliers in C (2004)
• Implemented the “Aurora” protocol, serializing the data stream at the transmitter, using 8B/10B encoding and decoding scheme and deserializing the data at the receiver side in Verilog (PCI-XBus Architecture -2003)
• Designed an interface between SCSI controller and PCI bus. Implemented different functionalities like Target Write, I/O Write and Initiator Write(PCI Bus Architecture-2002)
• Designed a prototype of 4-bit slice microcontroller using Verilog. Simulations were done using LSIM and layout was obtained using Mentor Graphics (VLSI Design - 2001)
• Designed and implemented chatting session via. synchronous serial interface (SPI) between two MC68HC12 microcontrollers. One microcontroller acts as master and generates the clock whereas other microcontroller acts as slave and uses the clock to latch data in or out (Microprocessors - 2001)
• Designed and Implemented musical keyboard synthesizer using VGA interface (FPGA/Verilog - 2001)
• Designed and implemented “Firefly” copy-back cache coherency protocolin Verilog (Cache System - 2001)
• Design and implemented a DFT-low pass filter on flash with Mic as input (DSP Implementation - 2005)

PAPER PUBLICTIONS

• P. A. Patel and C. J. Parikh, “IDEA Cryptographic Processor in FPGA”, Special Issue of the Journal Computational Methods in Sciences and Engineering
• Chirag Parikh and Parimal Patel, “Design and Implementation of AES (Rijndael) Algorithm”, 17th International Conference on Computer Applications in Industry and Education (CAINE-2004), pp 85-89, November 2004, Orlando, Florida

• P. Patel and C. Parikh, “Design and Implementation of AES (Rijndael) Algorithm”, 16th International Conference on Computers and Their Applications (CAINE-2003), November 2003, Las Vegas, NV
• P. Patel and C. Parikh, “An Efficient Design and Implementation of DES and Triple-DES Algorithms, 18th International Conference on Computers and Their Applications (CATA-2003), March 2003, Hawaii

ORGANIZATIONS

• Institute for Electrical and Electronic Engineers (IEEE)
• International Society for Computers and their Applications (ISCA)