3.4.2P State Machine Design VEX

Project 4.1.3State Machine Design:
Tollbooth (VEX-DLB)

Introduction

Now that you have seen examples of state machines and how they work, it is time for you to create your own. The state machine you will be designing is based on the tollbooth gate example. If you are a former PLTW Gateway student you might remember creating a similar design using the VEX® Cortex Controller and programming it with RobotC.

In this design you are required to use a PLD to create a functioning prototype. Can you think of any advantages to creating this design in simulation and exporting it to a PLD rather than using the VEX Cortex Controller?

The tollbooth gate state machine has four inputs and four outputs.

Inputs

Outputs

Equipment

• Circuit Design Software (CDS)
• Digital Logic Board (DLB)
• SN754410 Quadruple Half-H Driver or L298 H-Bridge Driver
• Resistors: (3) 100kΩ: (1) 180Ω: (1) 330Ω
• VEX Tollbooth Kit
• Variable power supply or (4) AA Batteries with holder
• #22 Gauge solid wire

Procedure

Design

Using the provided state graph and state transition table as a starting point, design a state machine that will control the opening and closing of the tollbooth. This state machine will be implemented in the FPGA on the DLB. Your design should clearly show how you will implement the following:

• Input Combinational Logic – What happens next based on the states of the buttons and switch inputs?
• Memory – How do you use flip-flops to create the number of states needed and to trigger the state transition when an input is made?
• Output Combinational Logic – Which motor output (Open/Close) and what LED indicator should come on to indicate the current state of the gate?

State Graph Analysis

From the provided state graph, you can see that the tollbooth design requires four states (S0-S3). The two state variables required have been identified as Qa and Qb. You should maintain these labels in your design. How did you know that two state variables were required for this design?

With each clock signal, the buttons and switches are checked to determine if the next state should be transitioned to or if there is no change in the state. Can you identify the physical state of the tollbooth based on the provided state graph?

State Transition Table Analysis

Now let’s look at how the State Transition Table was generated from the State Graph. For each state, there must be 4 sets of inputs that cause a transition. So with 4 possible states, there are actually 8 sets of inputs that must be checked on each clock signal to determine if the state is held or if a transition to the next state will take place.

In the first line of the transition table (S0), the gate is closed.

In the second line of the transition table (S0), the Open Switch Pushbutton is pressed by the operator.

Without looking at the notes on the previous page, begin on LINE 2 and see if you can accurately predict the NEXT STATE and the outputs as you move down each consecutive line. Below each line in the transition table is a box where you can describe (in your own words) what is happening at the tollbooth. The first few descriptions have been given as examples to get you started. After you have worked through the table you can go back and put in the “Don’t Care” comments.

Note: This handout is meant to be a tool that helps you understand the tollbooth state machine design. It is for your use only. You should be documenting all of your work for final evaluation in your engineering notebook or project portfolio.

Tollbooth State Transition Table Analysis

Design Equations

The input combinational logic to your flip-flops is represented by the NEXT STATE* on your transition table. That is, the Da and Db into your flip-flops are the same as the Qa* and the Qb* in your transition table. Therefore you should be able to generate two logic expressions from the INPUTS listed as a (logic one) for Qa* and Qb* respectively. See if you can generate the un-simplified expressions without referring to the previous page.

Input Combinational Logic

Da = Qa* =

Db = Qb* =

Capture these expressions in your engineering notebook and simplify into your own unique design.

There are 4 possible outputs: “Gate Closed Indicator”, “Motor Open Signal”, “Gate Open Indicator”, and “Motor Close Signal”. What are the logic expressions for these 4 outputs based on the transition table?

Output Combinational Logic

MO =

MC =

GO =

GC =

Simulation

Simulate the design in the CDS. Remember, you can simulate in PLD mode using the interactive digital constant for the switches and probes to represent the outputs.

Start the simulation with CL activated (logic one), while OB, OL, and CB are not activated (logic zero). This will simulate the gate closed and no buttons activated. In simulation, it is fine to use a low frequency clock signal (20 Hz or lower). Would this be a good idea when you actually create the prototype? Use the simulation to verify that your design works.

Prototyping

Create the tollbooth test fixture using the provided VEX structural components, (2) limit switches, and a 2-wire motor. Pictures of an example test fixture are provided.

In addition to creating the mechanical tollbooth test fixture, you will need to use additional components so that you can drive a DC motor using digital logic signals (L298 Dual Full-Bridge Driver or the SN754410 Quadruple Half-H Driver). VEX motors operate at voltages larger than the digital 5V used by TTL. It is also a good practice to use a different or back up voltage source for logic circuits that drive motors. Why do you think this is a good idea?

(NOTE: To protect the DLB, It is important to use an EXTERNAL power supply for the 6V necessary to drive the motor. Check that your external power supply and DLB share a common ground.)

Tollbooth Test Fixture – Build

Shown below are photographs of the front, back, and detail views of the Tollbooth test fixture. You will use this fixture to verify that your design is working.

Tollbooth Test Fixture – Wiring Diagram

The schematic shown below illustrates how you can interface the tollbooth test fixture with the Digital Logic Board (DLB). The L298 is an H-bridge driver designed to accept standard TTL logic levels and drive DC motors. Refer to the L298 Dual Full-Bridge Driver data sheet online for pin assignments. The open/close pushbuttons and open/close LED indicators are not included in the diagrams below. You will need to determine how to include them in your PLD design. (Note: Do not forget to assign a GPIO to your flip-flops in your PLD design and wire your RotCLK on the DLB so that you can send a variable clock signal.)

L298 H-Bridge Driver

The SN754410 Quadruple Half-H Driver can be used as an alternative to the L298.

SN754410 Quadruple Half-H Driver

Use the Digital Logic Board and the Tollbooth test fixture to build and test your state machine design. Verify that the circuit is working as designed. If the circuit is not working properly, review your design work and circuit implementation. Make any necessary corrections and retest. Document all changes in your engineering notebook.

Suggestion: Turn the DLB’s RotCLK a full turn to the right after programming the FPGA chip to adjust the frequency of the clock signal.

Conclusion

In your engineering notebook, write a conclusion (minimum 250 words) that describes the process you used to design, simulate and prototype your tollbooth state machine. This conclusion must include all of your design work, preliminary and final schematics, a parts list, and a digital photograph of your final circuit. The documentation should be complete enough that another student, with that same knowledge of digital electronics, could reproduce your design without any additional assistance.

© 2014 Project Lead The Way, Inc.

Digital Electronics Project 4.1.3 State Machine Design:Tollbooth (VEX-DLB) – Page 1