1Identification and Significance of the Opportunity

High Temperature (N05-012)

1Identification and significance of the opportunity

The current generation of air vehicle and propulsion systems can be characterized as centralized control systems in which a (redundant) central computer and centrally located analog signal interfacing circuitry is used to interface with sensors and actuators located throughout the aircraft and the propulsion system. A block diagram of this centralized architecture is shown infig. 1.0-1. In most instances, the digital computer implements the “control laws” while the analog circuitry is used for conditioning the inputs, outputs and for performing actuator loop closures etc. The types and quantities of sensors and actuators are unique to each system and therefore lead to an implementation that is new and unique for each new aircraft and engine. The cost of designing and maintaining these new systems is enormous. Numerous studies and concept papers {x-x} have shown the advantages of distributed open system architectures in which centralized computers communicate via standardized serial data buses with “smart” boxes, which are co-located with the sensors and actuators. The studies also suggest that such a distributed architecture would greatly reduce not only the total ownership cost(i.e. development costs plus acquisition and maintenance cost) but also significantly reduce the weight and fault diagnosis (i.e. detection and isolation) cost associated due to the simplification and standardization of the wire harnesses.Furthermore, the “smart” boxes would provide for anopen architecture and “standardized” bus oriented method for interfacing by thehost computer regardless of the signal conditioning and loop closure electronics specific to the actuator or sensor involved.Furthermore, new systems could then be easily and affordably assembled around a central processor by re-using these “smart” boxes. These benefits would be greatly enhanced if these “smart” boxes were somehow reconfigurable or more “generic” and can therefore reused for multiple sets of actuators and sensors.

Figure 1.0-1 Centralized Architecture with Custom Elements

There are two obstacles to the realization of such open and distributed air vehicle and propulsion system architectures containing “generic” Electronic Interface Modules for actuators. First, this open and distributed solution requires the “Generic” Electronic Modules (GEM) to co-locate and operate in harsher environments including the high temperature environments(~ 200 deg. C) associated with actuators. The thermal environment of future super-cruise air vehicle propulsion systems and flight control actuators is likely to be even more demanding. However, most electronic components, even industrial grade ones, only operate up to 125 deg. C. The lack of high temperature (~200 deg. C) parts was a major driver for the DARPA HiTeC (High Temperature Cooooo) program {x}, to be launched in 1998, and has led to the development of Silicon on Insulator (SoI) technology. The HiTeC program has led to thecommercial development of several High Temperature component families ( ??)with a basic set of analog and digital components that can continuously operate at High Temperatures (225 deg. C). Prominent among them is the HTMOS family from Honeywell ( offers several basic essential building blocks, such as microprocessors, memories for program, data and parameter storage, as well as Gate Arrays and Op. Amps., all of which are essential for building a generic electronic module. However the HTMOS family from Honeywell does lack, at least at this point, some key components such as an A/D converter.

The second obstacle to the realization of “generic” electronic modules is the diversity of the quantity and types of sensors (position, speed, pressure difference, temperature etc.) which makes it difficult to develop a “one size fits all” generic analog signal conditioning interfaces that can be “reused”. In the absence of such a capability, each electronic module would be custom to its specific actuator and sensors it was designed for. Even if such a custom electronic box was “open” with standards based interfaces, the cost of developing, procuring and maintaining it would once again be significant. Theproliferation and lack of reuse for such custom boxes would make the distributed open architecture approach very unattractive. Therefore, cost of ownershipbenefit of open systems architectures has created an urgent need for Generic Electronic Modules (GEM) which canoperate in High Temperature and which can be reused for multiple applications.

The key innovation in the proposed solution is the maximal digital implementation of the GEM, wherein all possible analog functions are digitally implemented making the functions reconfigurable. This emphasis on digital implementation is driven by two factors. First, digital implementations, especiallysoftware driven digital implementations are more re-usable because thesoftware permits the same hardware, without changes to be re-used for performing different functions (e.g. interfacing with different signal types). Second, it easier to make High temperature digital components than analog components becausethey require largerdie sizes and higher control of accuracy and leackage currents etc. Theproposed GEM therefore has the minimal but necessary analog “front ends” consisting basically of Op. amps, that can be reused for interfacing with adiverse group of analog sensor signals.

A key feature of the proposed solution is that the Generic Electronic Module (GEM) does not require any as-yet–not-developed new High Temperature devices. TheGEM can be fully implemented by using the available suite of high temperature electronic components as building blocks. For instance, the 12 bit, accurate, A/D converter, very difficult to implement as a monolithic device in high temperature, is constructed by using digital glue logic arounda 1 bit A/D converter, i.e., an op. amps,and a comparatorboth of which are readily available from the HTMOS family. Similarly, the generation of A/C excitation and demodulation needed for LVDT position sensors is done digitally involving only an op. amp. and the A/D converter. High speed data buses such as Mil-Std-1553 requiring bus transformers are replaced by simple serial buses such as RS-485 requiring op. amps and digital logic. Finally, software algorithms are used for digitally demodulating LVDT position signals thereby permitting the same analog “front end” to be re-used for interfacing with DC or AC analog signals. Similarly, combinations of op amps. and glue logic are used to create reusable interfaces for frequency and speed signals. Reconfiguration of the GEM thus only involves changing the algorithms to be used for interfacing with LVDT sensors, pressure sensors, temperature sensors and so on. The basic elements of this concept are sketched in fig. 1.0-2 in which the custom hardware components shown in fig. 1.0-1 are replaced with standard data buses and digitally reconfigurable interfaces.

Figure 1.0-2 Reconfigurable GEM Architecture

2Phase I Technical Objectives

The stated technical objectives of the Phase I program is to develop and demonstrate the feasibility and capabilities of an open systems solution to the general problem of lack of generic electronicinterfaces for actuators in extreme environments in air vehicles and propulsionsystems.

The concept of reconfigurable Smart Terminals, minus the High Temperature aspects, has been explored in the past,particularly, in the context of distributed flight control systems. The hardware and software design of the Smart Terminal is described in Section 4.0. The proposed program builds on the expertise and lessons learned from this work. The Smart Terminal was designed as a reconfigurable module for implementing the closed loop control of hydraulic actuators under the command of a host processor via a serial bus. This project successfully demonstrated, in the laboratory, the feasibility of digital demodulation of LVDT signals and digital generation of very accurate AC excitation needed by the LVDT actuator position sensors. The actuator commands were received over a RS-232 serial bus at 80 Hz and the position loop was digitally closed. The primary difference between that implementation and the requirements of the present topic is the High Temperature environment. Because the earlier project had no High Temperature requirements, it was built using industrial grade ICs. As such there was no need to construct basic building blocks such as an A/D or UART and or Bus Transceivers needed by the serial bus. Since these building blocks are not available in the library of HTMOS parts, they will have to be built using available components from the library of HTMOS and other families. The building blocks needed for this project will also have to include additional interfaces for frequency and pulse type input signals associated with pressure and temperature sensors, or torque motor position signals. However, a review of the HTMOS parts library give us confidence that these necessary interfaces canalso be built using the HTMOS family to meet the requirements of the High Temperature GEM.

3Phase I Work Plan

In view of this past experience base with the Smart Terminal, the program objectives will be appropriately tailored to focus on the building of these building blocks before integrating them into the design of the GEM.

3.1Interface Definition:

This task involves defining the interface characteristics, including electrical characteristics, accuracy and resolution etc. for a representative Generic Electronic Module (GEM). These interfaces will include selected classes of, inputs signals from actuator position sensors and associated equipment, output signals for actuators drives and associated equipment, along with interfaces for a data bus and for power received from the host. The input signal class will include the following signals:

1. DC and AC actuator position signals from hydraulic and/or EM actuators
2. Frequency signals from pressure and temperature sensors
3. Speed and frequency signals from torque motors and EM actuators ???
4. Analog or discrete switch position signals from contactors and solenoids

The output signal class will consist of the following signals:

1. Current drive signals for hydraulic actuators
2. H Bridge signals (with or without PWM) for torque motors and EM actuators
3. Shutoff and engage discrete signals for solenoids and switches

It should be pointed out that the proposed GEM does not include the final power drive stages for high power actuator drives for several reasons. First, these drive tend to consume a lot of power and generate lots of heat, which can adversely affect the temperature inside a GEMenclosure. Second, the interfaces tend to be quite specific to the type of actuator and including them in a GEM would not be consistent with its “generic” nature. Finally, the EMI treatment needed for some of these power stages tends to be quite elaborate (e.g. Tranzorbs) and tailored to the type of drive involved. It is believed that the actuator housing is therefore the best possible location for these power stages because the large mass and relatively steady temperature profiles at these sites provide significant reliability benefits for the electronics in spite of their high temperature environment. The best example of this reliability benefitis the FADEC engine controller which hasan excellent reliability in spite of their harsh environment because it is fuel cooled. In any case, the output(s) built into the GEM will be generic in design so that they can directly be connected to the power drive stages located at the actuators.

The serial data bus for the GEM will be the ubiquitous RS-232. This choice is primarily driven by the constraints of the HTMOS High Temperature chipsets available for implementation at this time. However, the choice is not much of a performance constraint because the commands to be sent over this bus from the host control computer are generated at no more than 100 Hz. This update rate is not likely to go up for super-cruise air vehicles because of inherent mechanical considerations. This update rate is distinctly different from the actuator inner loop closure rates which can be much higher (> 1000 Hz) especially for DDV actuators and the newer EM actuators on newer aircrafts such as JSF. In any case the RS-232 bandwidth achievable will depend on the speed and functions available from the High Temperature chips in the market. It is anticipated that the available chipsets will support development of a 9600 Baud RS-232 which can easily support the above command update rates.

This task will also define the aircraft power requirements for the GEM. Thepower requirements of the actuator power drive stages are too specific to the type of actuators involved and will not be addressed in this section.

3.2High Temperature Electronics Building Blocks:

This task will focus on building and testing the following major new building blocks in a standalone fashion:

1. A/D Converter: Typical actuator positional accuracy requirements are adequately met by a 12 bit A/D converter. TheHoneywell HTMOS library does not offer any A/D converter. A 10 bit A/D converter is under development at cissoid which is a fablesHigh Temperature SoI development company( the 12 bit A/D converter will have to be built up from the library of parts that are available. An A/D converter can be constructed in one of several ways. An A/D based on the Successive Approximation Register (SAR) method can be constructed (see fig. 3.2-1) using an Op amp., plus a comparator, precision D/A converter and a precision capacitor.Each ADC conversion is divided into two distinct phases as defined by the position of the switches shown in Fig. 3.2-1. During the sampling phase (with SW1 and SW2 in the “track” position), a charge proportional to the voltage on the analog input is developed across the input sampling capacitor. During the conversion phase (with both switches in the “hold” position), the capacitor DAC is adjusted via the SAR logic until the voltage on node A is zero, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor DAC. The digital value finally contained in the SAR is then latched out as the result of the ADC conversion. Control of the SAR, and timing of acquisition and sampling modes, is handled by the ADC control logic. Clearly the acquisition and conversion times of the SAR method will require fine tuning in order to meet the rapid sampling requirements of the A/D within the limitations of the HTMOS family.

Figure 3.2-1 Precision Capacitor based Successive Approximation A/D

A second method for implementing an A/D converter involves a simple latter network which is driven by the processor and whose output is compared with the external analog voltage (see fig. 3.2-2). The final selection of the method used for implementing the A/D will be made during the design process. In any case the complete A/D design will be built and tested in a stand-alone fashion to ensure that it meets the performance requirements (sampling time, accuracy, Sample and Hold times etc.) before proceeding to task 3.2.

Figure 3.2-2Ladder Network based Successive Approximation A/D

1. RS-232 UART and Transceivers: In the simplest form, the RS-232 transceivers are voltage level translators that convert signals from UART (Universal Asynchronous Receiver/ Transmitter) at TTL to the serial bus levels (5V to 15 V). As such they can be constructed using the op. amps. available from the High Temperature parts library. The HTMOS micro controller (HT83C51) contains a UART for communication between the processor and a remote host. The documentation for the device states that it is capable of half duplex (either transmit or receive but not both at the same time) communication, which is acceptable for our application. If the speed of the UART is not adequate to support our bandwidth needs, an external UART can be built. This design of a UART is well documented in the literature {x}and can be implemented using the High Temperature chipsets available. In this design, the incoming signal is sampled by the UART at up to 6 times the signal baud rate to detect a logic “1” or “0” which is then shifted into a register. When 8 continuous bits are recognized and received into the shift register, they are moved into a buffer and monitoring of the bus for new bits is started. The host processor is notified via an interrupt when the buffer is full. On the output side, a byte of data is continuously shifted out at the prescribed rate from the shift register loaded by the host processor.In any case the complete RS-232 design, including the UART and the transceivers, will be built and tested in a stand alone fashion to ensure that it meets the performance requirements (data bandwidth, error rates etc.) before proceeding to task 3.2.
2. Frequency and Pulse signal Conditioning: These type of signals usually associated with pressure sensors and sometimes even temperature sensors. Regardless, in most such instances, the value of the signal is proportional to the number of signal pulses received in a fixed time duration. The implementation of the interface for such signal is shown is shown in fig. 3.2-3 and is quite straight forward and consists of counting the number of pulses from the signal as well from an accurate time reference signal such as a clock. In most instances, the ratio of the two counts is proportional to the pressure or temperature. The digital portion of this implementation is anticipated to fit in one Gate Array in the HTMOS family.

Figure 3.2-3 Generic Frequency and Pulse Conditioning Interface