COEN6501 FINAL, FALL 2006

Q1) 12 bit Carry Ripple Adder

Delay = 12

Area = 12

Power

Now the 12 bit carry select adder can be designed either using 3 – 4bit adder or 4 – 3 bit adders. Kopt

Option 1.

4 * 3 bit adder

Delay = Assuming

mux is 2 -> 1 mux

Area =

Option 2.

3 * 4 bit adder

Delay =

Area =

Selection is based on minimum delay, therefore option 1 is selected.

Comparison / Area / Delay / Power
Ripple / / /
CSA / / /

Delay is almost 1/3-60%

Area is almost double +100%

Power is almost double +100%

Q2)Implement ,

Let

x3 / x2 / x1 / x0
x3 / x2 / x1 / x0
x3 x0 / x2 x0 / x1 x0 / x0 x0
x3 x1 / x2 x1 / x1 x1 / x0 x1
x3 x2 / x2 x2 / x1 x2 / x0 x2
x3 x3 / x2 x3 / x1 x3 / x0 x3
x3 / x3 x1 / x0 x3 / x2 x0 / x1 x0 / 0 / x0 /
x3 x2 / x2 x1 / x1
x2
x3 / x2 / x1 / x0 / 4x
x2 / 1 / 2

Using the following simplifications: xi*xi=xi; xi*xj=xj *xi; xiplus xi=2xi; xi+ xj=2xij

Delay=4.5

Area=5Afull-adder+3Ahalf-adder+6AND

Q3)

State Diagram (Moore circuit)

States assignment:

Let / y1 / y0
S0= / 0 / 0
S1= / 0 / 1
S2= / 1 / 0
S3= / 1 / 1

State Table:

CurrentState / NextState / Output
y1 / y0 / y+1 / y+0 / w / x / y / z
0 / 0 / 0 / 1 / 0 / 1 / 0 / 1
0 / 1 / 1 / 0 / 1 / 0 / 1 / 1
1 / 0 / 1 / 1 / 0 / 1 / 1 / 0
1 / 1 / 0 / 0 / 1 / 0 / 0 / 1

State equations:

Output equations:

Q4)

To select minimal implementation. There are several ways, applying Shannon’s expansion.

First since we are using ACT1 module1, the delay is fixed, the area is fixed and power can be minimized.

The power can be minimized by using minimum component and less switching. We can expand by A or B or C or D.

Variable A

Variable B

Variable C

Variable D

MINIMAL IMPLEMENTATION

Q4b)

Q5)

a) There are 9 paths in the circuit. In this, the choice is obvious.

The critical path is D4 → X2 (or X1) → N1→ D1

X2 and X1 have the same delay generated since it has the same fan-out and intrinsic delay.

b)

c)

Assume total skew is -2

Total derating factor = 1.16

We will assume Clock skew between any 2 FFs is -2 constant. (If we take clock skew of -2 between successive FFs, then the critical path has to be recalculated and path D5 → X1 → N1→ D1 is the critical path since skew will be -8. T=15.06nS and f=66.4 MHz)

If we take for any successive FFs, then T=5.93ns – (–2) =7.93nS or T=7.93 * 1.16 = 9.21nS.

f=1/7.93 without temp effect

f=1/9.21 =108MHz with tem effect

Assume clock skew between any flip flop

Q6)

a)

L5 / It should have been std_logic_vector
L6 / It should have been std_logic_vector
L8 / B_Encoder should be Booth_Encoder, also “is” is missing
L9 / Std_logic_vector(54 downto 0)
L14 / Begin is missing
L15 / For i in 0 to 26 loop
L25 / Missing ;
L20 / Is acceptable practice

b) This circuit is an Encoder with truth-table

Ein(3) / Ein(2) / Ein(1) / Ein(0) / Eout(1) / Eout(0)
1 / x / x / x / 1 / 1
x / 1 / x / x / 1 / 0
x / x / 1 / x / 0 / 1
x / x / x / 1 / 0 / 0

c)

The circuit is a special MUX or selector. Depending on input “Sel”, output y is one of the inputs “x1”, “x2”, “x3”, “x4” & “x5”. These values are select if “Sel” is “000”, “001”, “010”, “011” or “100”, the default output is x3.