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Next Generation OPC -- Mentor Graphics Corp., announced availability of Calibre nmOPC, a third-generation optical proximity correction (OPC) tool that expands the Calibre arsenal of resolution enhancement technology (RET) products for sub-65 nanometer (nm) process technologies.

Low k1 photolithography processes are increasing the complexity of RET applications in nanometer designs. At 45nm, more complex models and through process window correction and verification requirements significantly increase computational burden. Both the lithographic challenges and the computational complexity associated with the 45nm process node create a need for advanced capabilities for computational lithography tools.

Calibre nmOPC answers these challenges by delivering several innovations including dense simulation, process window optimized OPC, a hybrid computing platform utilizing co-processor acceleration (with the Cell BE processor), a new compact resist process modeling capability, and design-intent aware correction algorithms. The tool runs on the fully integrated Calibre hierarchical geometry engine uniquely enabling a fully integrated design to mask flow with a unified command language. The tool also delivers many practical production features such as: OASIS formatting to minimize output file size; new streamlined hierarchical processing to improve run time and file size compared to flat OPC tools, a progress meter and dynamic CPU allocation capability to manage TAT in a production environment.

Process variability can have a dramatic effect on yield. This is especially true in the lithographic process where dose and focus variability impacts image fidelity. To reduce the risk of silicon failure and enable acceptable yield under challenging low k1 conditions, Calibre nmOPC uses both dense simulation capabilities, which provide 100 percent simulation coverage for the mask layer, and process window correction optimization algorithms to ensure silicon-patterning success. The tool also features multi-layer inputs into the correction algorithm to enable design critical features to be patterned to preserve design intent and parametric yield.

The company addresses the rising cost of ownership associated with the geometrically increasing need for more CPUs by introducing a unique CoProcessor Architecture. The Remote Acceleration Simulation (RAS) architecture elegantly enables the option of connecting a Coprocessor Acceleration cluster with an Ethernet connection to an existing compute cluster. Mentor has partnered with Mercury Computer Systems, a provider of high performance computing system design, to offer standard Coprocessor Acceleration clusters based on the ultra-high performance Cell Broadband Engine (CBE). The Cell Processor clusters accelerate the image processing components of Calibre nmOPC enabling 4 to 10X improvements in run time with little to no increase in general purpose computing requirements over the 65nm node. This innovative application of the Cell Processor to computational lithography will reset cost of ownership targets for the industry in line with customer requirements for cost mitigation. To learn more, visit the respective company websites at: and www-128.ibm.com/developerworks/power/cell/index.html.

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Core-Optimized IP Kits -- Virage Logic Corp., a provider of semiconductor intellectual property (IP) platforms, and MIPS Technologies, Inc. recently announced instant, easy access to a series of jointly developed Core-Optimized IP Kits via Virage Logic's website (see below). Leveraging Virage Logic's Area, Speed and Power (ASAP) Memory and ASAP Logic High-Speed (HS) IP, the series of Core-Optimized IP Kits introduced earlier this year provides MIPS Technologies' customers with IP that is specifically tuned to enhance the performance of MIPS processor cores.

The Core-Optimized IP Kits target the MIPS32, 24K, 24KE and 34K families of processor cores for manufacture on TSMC's 90-nanometer (nm) G process. The 24K and 24KE processor core families can achieve clock frequencies of 660 MHz, using only nominal threshold transistors when implemented with the Core-Optimized IP Kits.

The MIPS32 24K and 24KE core families offer performance of 660 MHz in a 90 nanometer G process, while minimizing design time and reducing product costs. These processor cores are suited to embedded consumer applications such as digital and interactive TVs, set-top boxes and DVD players. The 24KE cores integrate the company’s DSP Application-Specific Extension (ASE), providing up to 3x the signal processing performance over a range of embedded applications, when compared to RISC implementations without the DSP ASE.

The 34K core family is the first series of licensable MIPS cores that offers SoC designers a superior hardware multi-threading solution to boost system performance while significantly reducing overall SoC die area, cost, and power consumption. The 34K cores are designed to mask the effect of memory latency and other short-term pipeline stalls by increasing processor utilization.

Virage Logic's Core-Optimized IP Kits are specifically tuned to maximize the performance of a target processor. The 24K and 24KE processor families will hit clock frequencies of 660 MHz when implemented with the Core-Optimized IP Kit, which includes the company’s ASAP Memory High-Speed (HS) instances and ASAP Logic HS standard cell libraries. To learn more, visit the respective company websites at: and

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Video Processor Engines -- Tensilica, Inc. just introduced four new Diamond Standard VDO (ViDeO) processor engines customized for multi-standard, multi-resolution video in System-on-Chip (SOC) designs. Targeted at mobile handsets and personal media players (PMPs), these video subsystems are fully programmable to support all popular VGA and standard definition (SD, also known as D1) video codecs with resolutions up to 720x480 (NTSC) and 720x576 (PAL) including H.264 Main Profile, VC-1 Main Profile, MPEG-4 Advanced Simple Profile (ASP), and MPEG-2 Main Profile, each of which is available from Tensilica. Lower resolutions such as QCIF, QVGA, CIF and VGA are also supported.

The Diamond Standard VDO engines host all the key video processing functions in software on the cores – including the network abstraction layer, picture layer, slice layer, bit-stream parsing and entropy decoding and encoding. This includes the computationally demanding CABAC (Context Adaptive Binary Arithmetic Coding) decoding in the H.264 Main profile decoder that most other solutions omit, implement in a separate and complex non-programmable hardware block or necessitate more than 700 MHz of general CPU workload which significantly increases power consumption. By implementing CABAC in instruction set extensions, Tensilica was able to create a low MHz and power efficient version of CABAC in less than half the area of a typical CABAC hardware block.

The Diamond VDO family offers both Baseline and Main profile solutions – Main profile offers superior data compression and video quality and is the preferred coding scheme at resolutions of D1 and higher for advanced handset and PMP applications. Most other video solutions for SOC design only implement Baseline profile video.

Four different Diamond Standard VDO engines are being introduced to meet the varying needs of the market.

To build the new Diamond Standard VDO family Tensilica used its Xtensa configurable and extensible processor technology to create a dual-processor subsystem block, complete with an integrated DMA engine, that delivers full D1 Main profile decoding and ASP encoding at extremely low clock rates (needing only 172 MHz for full H.264 Main profile decode, and only 156 MHz for MPEG-4 ASP decode).

The Diamond Standard VDO family is optimized for mobile applications and requires a smaller area and consumes less power than competing solutions. Through the use of fine grained clock gating, a feature of the Xtensa processor architecture, and the integration of power management instructions which provide programmability to throttle power under varying video work loads, active power is further minimized. Additional power efficiency is achieved through the implementation of the DMA engine and interface to the Stream and Pixel Processors that minimizes the external memory bandwidth requirements. To learn more, visit the company website at:

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I/O Optimized FPGAs -- Xilinx, Inc. has unveiled its Spartan-3A family of I/O-optimized field programmable gate arrays (FPGAs), an extension of its low-cost, high volume Spartan-3 Generation. The Spartan-3A platform provides a cost-reduced solution for applications where I/O count and capabilities matter more than logic density. With support for the industry’s widest range of I/O standards (26) and unique power, configuration capabilities and anti-cloning security advantages, Spartan-3A FPGAs provide a flexible and cost-saving solution to new high-volume applications within consumer and industrial segments, such as display panel interfaces, video/tuner board interfaces and video switching.

With the addition of an I/O-optimized platform, the Spartan-3 Generation expands the billion-dollar global market for low-cost FPGAs targeting volume applications on the ‘edge of the network’ in the home, in the car and on the factory floor. Consumer and wireless products such as flat panel displays, wireless networks, residential gateways, and IP set top boxes represent a $280 million PLD market opportunity in Asia Pacific, a region in which the Spartan-3 Generation has recorded an annualized growth rate of 275 percent through the most recent (Q2FY07) quarter. Video security and robotic products are among the applications fueling demand in industrial sectors, particularly in Europe.

Built on 90nm technology, the new platform consists of five devices offering up to 1.4 million system gates and 502 I/Os. Offering the lowest cost per I/O in the industry, the new family also features significant advances in power management, device configuration and design security. The Spartan-3A platform integrates an array of innovative features and technologies including – among other things - the widest I/O Standards Support. The company claims that it is the first TMDS-compliant FPGAs enabling DVI and HDMI support for consumer video applications, and the only FPGAs compliant to 26 popular single-ended and differential signaling standards. Source-synchronous interfacing technology cost-optimized to ensure best design margins. Pre-engineered solutions for PCI, PCI Express, USB, Firewire, CAN and SPI among others, as well as support for all popular low-cost DDR and DDR2 memory interfaces up to 333 Mbps. To learn more, visit the company website at:

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Multi-Core Platform -- Teja Technologies Inc., recently announced that Sun Microsystems, Inc. has selected the Teja NP Software Platform for its Network Data Plane Suite (NDPS). Using the NDPS in conjunction with Sun’s Netra servers and ATCA blades incorporating the UltraSPARC T1 processor with CoolThreads technology, network equipment providers can rapidly develop advanced, high-performance data plane applications.

Under the agreement, Sun will leverage a version of Teja’s software platform for multi-core applications for its NDPS suite. Sun’s NDPS suite is targeted at network equipment providers using Netra servers and ATCA blades for advanced telecommunications data plane applications.

The NDPS suite is available from Sun for their new Netra line of UltraSPARC T1 ATCA blades and rack servers featuring CoolThreads technology executing 32 simultaneous processing threads.

Teja’s approach to embedded networking applications greatly simplifies development of software for parallel, multiprocessing architectures. An OEM’s primary challenge in designing with these types of systems is in properly partitioning the application code among the multiple processors, allocating shared memory resources, and building a framework to support scheduling, inter-processor communication and synchronization. Teja NP gives OEMs the ability to define a complete system’s application logic in hardware-independent C code and map it separately to the various resources of the target hardware configuration, resulting in the automatic generation of validated and optimized production code for the target system. The benefits of using Teja NP include the development of reliable, high-performance and scalable products that provide OEMs with a first-to-market advantage with significant reduction in engineering risk. To learn more about Teja, visit the company website at: To learn more about sun, visit:

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Programmable Power Technology -- Altera Corporation has announced its Stratix III FPGA family, which the company claims will deliver the industry’s lowest power consumption of any high-density, high-performance programmable logic device. Built on TSMC’s 65nm process, the FPGAs featurehardware architecture advancements and Quartus II software enhancements. Working together, the company claims that these new features deliver 50 percent lower power, 25 percent higher performance and 2x the density compared to previous generation Stratix II devices.

The FPGAs feature two new technologies that dramatically lower power while meeting high-performance requirements. Reduced power consumption is achieved by utilizing the company’s Programmable Power Technology, which maximizes performance where needed while delivering the lowest power elsewhere in the design. Programmable Power Technology enables every programmable logic array block (LAB), DSP block and memory block to independently operate at high-speed or low-power mode. The PowerPlay feature in Quartus II software version 6.1 automatically analyzes the design and identifies which blocks are in the critical path and demand the highest performance, setting these to high-speed mode. All other logic is automatically put into low-power mode. The second power-optimizing feature, Selectable Core Voltage, provides the designer options to select either 1.1V for designs needing the highest performance or 0.9V for designs requiring minimum power consumption.

The FPGA devices offer the highest memory-to-logic ratio and DSP performance compared to any other FPGAs in the industry, claims the company. To address a full range of high-end applications, three new Stratix III family variants are offered: one delivering balanced logic, memory and DSP resources for general-purpose applications, a second providing enhanced memory and DSP resources for memory- and DSP-intensive applications and a third offering integrated transceivers for high-bandwidth interface applications. Additionally, the company provides a unique and risk- free migration path from Stratix III FPGAs to HardCopy structured ASICs.

The Stratix III features include – among other things – programmable power technology; selectable core voltages; improved throughput speed; and high density.

In addition to the Quartus II design software, tools from leading EDA vendors Aldec, Inc. (System Verification Environment (SVE)), Magma Design Automation Inc. (Blast FPGA), Mentor Graphics Corporation (Precision Synthesis) and Synplicity, Inc. (Synplify Pro FPGA synthesis and Synplify DSP software) all support the Stratix III device family. To learn more, visit the company website at: