With the rapid development of integrated circuits (ICs), new problems were encountered and new solutions were developed. One of the problems with DTL circuits was that it takes as much room on the IC chip to construct a diode as it does to construct a transistor. Since "real estate" is exceedingly important in ICs, it was desirable to find a way to avoid requiring large numbers of input diodes. But what could be used to replace many diodes?
Well, looking at the DTL NAND gate to the right, we might note that the opposed diodes look pretty much like the two junctions of a transistor. In fact, if we were to have an inverter, it would have a single input diode, and we just might be able to replace the two opposed diodes with an NPN transistor to do the same job.
In fact, this works quite nicely. The figure to the left shows the resulting inverter.
In addition, we can add multiple emitters to the input transistor without greatly increasing the amount of space needed on the chip. This allows us to construct a multiple-input gate in almost the same space as an inverter. The resulting savings in real estate translates to a significant savings in manufacturing costs, which in turn reduces the cost to the end user of the device.
One problem shared by all logic gates with a single output transistor and a pull-up collector resistor is switching speed. The transistor actively pulls the output down to logic 0, but the resistor is not active in pulling the output up to logic 1. Due to inevitable factors such as circuit capacitances and a characteristic of bipolar transistors called "charge storage," it will take a certain amount of time for the transistor to turn completely off and the output to rise to a logic 1 level. This limits the frequency at which the gate can operate.
The designers of commercial TTL IC gates reduced that problem by modifying the output circuit. The result was the "totem pole" output circuit used in most of the 7400/5400 series TTL ICs. The final circuit used in most standard commercial TTL ICs is shown to the right. The number of inputs may vary — a commercial IC package might have six inverters, four 2-input gates, three 3-input gates, or two 4-input gates. An 8-input gate in one package is also available. But in each case, the circuit structure remains the same.
Resistor-Transistor LogicConsider the most basic transistor circuit, such as the one shown to the left. We will only be applying one of two voltages to the input I: 0 volts (logic 0) or +V volts (logic 1). The exact voltage used as +V depends on the circuit design parameters; in RTL integrated circuits, the usual voltage is +3.6v. We'll assume an ordinary NPN transistor here, with a reasonable dc current gain, an emitter-base forward voltage of 0.65 volt, and a collector-emitter saturation voltage no higher than 0.3 volt. In standard RTL ICs, the base resistor is 470 and the collector resistor is 640.
When the input voltage is zero volts (actually, anything under 0.5 volt), there is no forward bias to the emitter-base junction, and the transistor does not conduct. Therefore no current flows through the collector resistor, and the output voltage is +V volts. Hence, a logic 0 input results in a logic 1 output.
When the input voltage is +V volts, the transistor's emitter-base junction will clearly be forward biased. For those who like the mathematics, we'll assume a similar output circuit connected to this input. Thus, we'll have a voltage of 3.6 - 0.65 = 2.95 volts applied across a series combination of a 640 output resistor and a 470 input resistor. This gives us a base current of:
2.95v / 1110 = 0.0026576577 amperes = 2.66 ma.
RTL is a relatively old technology, and the transistors used in RTL ICs have a dc forward current gain of around 30. If we assume a current gain of 30, 2.66 ma base current will support a maximum of 79.8 ma collector current. However, if we drop all but 0.3 volts across the 640 collector resistor, it will carry 3.3/640 = 5.1 ma. Therefore this transistor is indeed fully saturated; it is turned on as hard as it can be.
With a logic 1 input, then, this circuit produces a logic 0 output. We have already seen that a logic 0 input will produce a logic 1 output. Hence, this is a basic inverter circuit.
As we can see from the above calculations, the amount of current provided to the base of the transistor is far more than is necessary to drive the transistor into saturation. Therefore, we have the possibility of using one output to drive multiple inputs of other gates, and of having gates with multiple input resistors. Such a circuit is shown to the right.
In this circuit, we have four input resistors. Raising any one input to +3.6 volts will be sufficient to turn the transistor on, and applying additional logic 1 (+3.6 volt) inputs will not really have any appreciable effect on the output voltage. Remember that the forward bias voltage on the transistor's base will not exceed 0.65 volt, so the current through a grounded input resistor will not exceed 0.65v/470 = 1.383 ma. This does provide us with a practical limit on the number of allowable input resistors to a single transistor, but doesn't cause any serious problems within that limit.
The RTL gate shown above will work, but has a problem due to possible signal interactions through the multiple input resistors. A better way to implement the NOR function is shown to the left.
Here, each transistor has only one input resistor, so there is no interaction between inputs. The NOR function is performed at the common collector connection of all transistors, which share a single collector load resistor.
This is in fact the pattern for all standard RTL ICs. The very commonly-used µL914 is a dual two-input NOR gate, where each gate is a two-transistor version of the circuit to the left. It is rated to draw 12 ma of current from the 3.6V power supply when both outputs are at logic 0. This corresponds quite well with the calculations we have already made.
Standard fan-out for RTL gates is rated at 16. However, the fan-in for a standard RTL gate input is 3. Thus, a gate can produce 16 units of drive current from the output, but requires 3 units to drive an input. There are low-power versions of these gates that increase the values of the base and collector resistors to 1.5K and 3.6K, respectively. Such gates demand less current, and typically have a fan-in of 1 and a fan-out of 2 or 3. They also have reduced frequency response, so they cannot operate as rapidly as the standard gates. To get greater output drive capabilities, buffers are used. These are typically inverters which have been designed with a fan-out of 80. They also have a fan-in requirement of 6, since they use pairs of input transistors to get increased drive.
We can get a NAND function in either of two ways. We can simply invert the inputs to the NOR/OR gate, thus turning it into an AND/NAND gate, or we can use the circuit shown to the right.
In this circuit, each transistor has its own separate input resistor, so each is controlled by a different input signal. However, the only way the output can be pulled down to logic 0 is if both transistors are turned on by logic 1 inputs. If either input is a logic 0 that transistor cannot conduct, so there is no current through either one. The output is then a logic 1. This is the behavior of a NAND gate. Of course, an inverter can also be included to provide an AND output at the same time.
The problem with this NAND circuit stems from the fact that transistors are not ideal devices. Remember that 0.3 volt collector saturation voltage? Ideally it should be zero. Since it isn't, we need to look at what happens when we "stack" transistors this way. With two, the combined collector saturation voltage is 0.6 volt -- only slightly less than the 0.65 volt base voltage that will turn a transistor on.
If we stack three transistors for a 3-input NAND gate, the combined collector saturation voltage is 0.9 volt. This is too high; it will promote conduction in the next transistor no matter what. In addition, the load presented by the upper transistor to the gate that drives it will be different from the load presented by the lower transistor. This kind of unevenness can cause some odd problems to appear, especially as the frequency of operation increases. Because of these problems, this approach is not used in standard RTL ICs.
Emitter-Coupled LogicEmitter-Coupled Logic is based on the use of a multi-input differential amplifier to amplify and combine the digital signals, and emitter followers to adjust the dc voltage levels. As a result, none of the transistors in the gate ever enter saturation, nor do they ever get turned completely off. The transistors remain entirely within their active operating regions at all times. As a result, the transistors do not have a charge storage time to contend with, and can change states much more rapidly. Thus, the main advantage of this type of logic gate is extremely high speed.
The schematic diagram shown here is taken from Motorola's 1000/10,000 series of MECL devices. This particular circuit is of one 4-input OR/NOR gate. Standard voltages for this circuit are -5.2 volts (VEE) and ground (VCC). Unused inputs are connected to VEE. The bias circuit at the right side, consisting of one transistor and its associated diodes and resistors, can handle any number of gates in a single IC package. Typical ICs include dual 4-input, triple 3-input, and quad 2-input gates. In each case, the gates themselves differ only in how many input transistors they have. A single bias circuit serves all gates.
In operation, a logical ouput changes state by only 0.85 volt, from a low of -1.60 volts to a high of -0.75 volt. The internal bias circuit supplies a fixed voltage of -1.175 volts to the bias transistor in the differential amplifier. If all inputs are at -1.6 volts (or tied to VEE), the input transistors will all be off, and only the internal differential transistor will conduct current. This reduces the base voltage of the OR output transistor, lowering its output voltage to -1.60 volts. At the same time, no input transistors are affecting the NOR output transistor's base, so its output rises to -0.75 volt. This is simply the emitter-base voltage, VBE, of the transistor itself. (All transistors are alike within the IC, and are designed to have a VBE of 0.75 volt.)
When any input rises to -0.75 volt, that transistor siphons emitter current away from the internal differential transistor, causing the outputs to switch states.
The voltage changes in this type of circuit are small, and are dictated by the VBE of the transistors involved when they are on. Of greater importance to the operation of the circuit is the amount of current flowing through various transistors, rather than the precise voltages involved. Accordingly, Emitter-Coupled Logic is also known as Current Mode Logic (CML). This is not the only technology to implement CML by any means, but it does fall into that general description. In any case, this leads us to a major drawback of this type of gate: it draws a great deal of current from the power supply, and hence tends to dissipate a significant amount of heat.
To minimize this problem, some devices such as frequency counters use an ECL decade counter at the input end of the circuitry, followed by TTL or high-speed CMOS counters at the later digit positions. This puts the fast, expensive IC where it is absolutely required, and allows us to use cheaper ICs in locations where the signal will never be at that high a frequency.
CMOS LogicCMOS logic is a newer technology, based on the use of complementary MOS transistors to perform logic functions with almost no current required. This makes these gates very useful in battery-powered applications. The fact that they will work with supply voltages as low as 3 volts and as high as 15 volts is also very helpful.
CMOS gates are all based on the fundamental inverter circuit shown to the left. Note that both transistors are enhancement-mode MOSFETs; one N-channel with its source grounded, and one P-channel with its source connected to +V. Their gates are connected together to form the input, and their drains are connected together to form the output.
The two MOSFETs are designed to have matching characteristics. Thus, they are complementary to each other. When off, their resistance is effectively infinite; when on, their channel resistance is about 200. Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.
When input A is grounded (logic0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has a channel enhanced within itself. This channel has a resistance of about 200, connecting the output line to the +V supply. This pulls the output up to +V (logic1).
When input A is at +V (logic1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.
This concept can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. The circuit to the right is a practical example of a CMOS 2-input NOR gate.
In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.
The structure can be inverted, as shown to the left. Here we have a two-input NAND gate, where a logic0 at either input will force the output to logic1, but it takes both inputs at logic1 to allow the output to go to logic0.
This structure is less limited than the bipolar equivalent would be, but there are still some practical limits. One of these is the combined resistance of the MOSFETs in series. As a result, CMOS totem poles are not made more than four inputs high. Gates with more than four inputs are built as cascading structures rather than single structures. However, the logic is still valid.
Even with this limit, the totem pole structure still causes some problems in certain applications. The pull-up and pull-down resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either P-channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable.
One of the main problems with CMOS gates is their speed. They cannot operate very quickly, because of their inherent input capacitance. B-series devices help to overcome these limitations to some extent, by providing uniform output current, and by switching output states more rapidly, even if the input signals are changing more slowly.
Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here.
One type of gate, shown to the left, is unique to CMOS technology. This is the bilateral switch, or transmission gate. It makes full use of the fact that the individual FETs in a CMOS IC are constructed to be symmetrical. That is, the drain and source connections to any individual transistor can be interchanged without affecting the performance of either the transistor itself or the circuit as a whole.
When the N- and P-type FETs are connected as shown here and their gates are driven from complementary control signals, both transistors will be turned on or off together, rather than alternately. If they are both off, the signal path is essentially an open circuit — there is no connection between input and output. If they are both on, there is a very low-resistance connection between input and output, and a signal will be passed through.