Frequency-Dependent Modeling of On-Chip Inductors on Lossy Substrates

Yun Bai, Zeynep Dilli, Neil Goldsman, and George Metze

Dept. of Electrical and Computer Engineering, U. of Maryland, College Park

College Park, MD 20742, USA

The trend for complete system integration on a single chip for RF circuits has recently led to a concerted research effort to obtain novel on-chip spiral, multilayer and 3-D inductors with large L, small area, low loss and high Q [1]. This requires modeling the inductance characteristics of such structures accurately and efficiently for automated design. Here, we describe recent work on the numerical modeling of on-chip inductor structures, applied to the comparison of inductor geometries. Two main physical phenomena must be considered for the frequency-dependence of inductor characteristics: Skin effect in the conductors [2] and induced currents in the semiconductor substrate [3].

Modeling On-chip inductors are fabricated by laying out spiral configurations using the metal layers available in IC processes. Inductors with different shapes and inductors that utilize multiple metal layers with different configurations have been investigated [1,4,5]. Our modeling approach, expandable to these different structures, is to treat each linear portion of the inductor as a distinct current segment (Fig.1) and investigate the internal and external self-inductance of each segment, as well as the mutual inductance between the segments, individually. These values are later combined into an inductance matrix [8], in which the diagonal terms represent self-inductances and off-diagonal elements are the mutual inductances:

(1)

The internal inductances of the segments arise from the frequency-dependent current density distribution within the conductor cross-section, found by solving the complex Helmholtz equation with the simplifying assumptions that there is only axial current in a good conductor, and that the current density variation in the thickness dimension of the interconnect is negligible[6]. The frequency-dependence of this component arises from the skin depth effect of the conductors. The external inductances of the segments are caused by the magnetic flux leakage from the interconnect segment, as the current and its return current either on a ground plane or distributed through the lossy substrate form a loop. The substrate currents vary with doping and frequency, requiring an analysis dependent on both factors. It has been shown that these effects can be represented by an image current separated from the original current by a complex distance [7]. This approach is also used when calculating the mutual inductance between segments, where the current loops formed by each segment and its complex image are subject to the flux linkage of the other segments.

Simulation Using process parameters typical for a 0.25 CMOS process, we simulated the performance of different spiral configurations to achieve an insight and verify the intuitive rules of thumb obtained empirically. Expectably, increasing the length of the inductor increases inductance, but leads to a decline in Q due to increasing serial resistance as well, this effect worsening at higher frequencies as skin effect increases the resistance faster than linearly with length. Increasing the number of turns is a better method to increase inductance, as this skin effect variation becomes less detrimental (Fig. 2). Decreasing the line spacing increases the inductance, as does decreasing the line width while keeping the spacing constant. It should be kept in mind, though, that the former method will probably increase parasitic capacitive coupling between turns and the latter increases the parasitic resistance. The effect of a semiconductor substrate on inductor performance can be observed by varying the substrate doping (Fig. 3). As doping increases, more current flows in the substrate rather than on the ground plane, approaching the metal layers with increasing frequency, so impedance becomes more frequency-dependent.

Figure 2 Inductance (in nH) of three spiral inductors with four turns and different lengths (left), and with the same length but different number of turns, vs. frequency, 1-10 GHz. Resistance vs. frequency plots are not shown to preserve space.

Figure 3 Inductance (nH) and resistance () of four spiral inductors with different substrate dopings (1016 to 1019) vs. frequency, 1-10 GHz.

Due to the versatility of the inductance matrix method, our simulator can be used to compare planar spiral inductors with stacked inductors with different configurations. Increased mutual inductance lets such inductors to have a higher inductance per length than their planar counterparts. It is also possible to investigate the mutual coupling between spiral inductors, and the dependency of such coupling to substrate doping should provide more interesting insights into on-chip physics.

References

  1. Bughartz, J.N, Rajaei, B., “On the Design of RF Spiral Inductors on Silicon,” IEEE Transactions on Electron Devices,v. 50, no.3, March 2003, pp.718-729.
  2. Ramo, S., Whinnery, J.R., van Duzer, T. Fields and Waves in Communication Electronics. 2nd Ed., John Wiley & Sons, USA 1984.
  3. Hasegawa, H., Furukawa, M. et al., “Properties of Microstrip Line on Si-SiO2 System,” IEEE Transactions on Microwave Theory and Techniques, v. 19, no. 11, November 1971, pp. 869-881.
  4. Zolfaghari, A., Chan, A., Razavi, B., “Stacked Inductors and Transformers in CMOS Technology,” IEEE Journal of Solid-State Circuit,, v. 36, no.4, April 2001, pp.620-628.
  5. Tang, C.-C., Wu, C.-H., Liu, S.-I., “Miniature 3-D Inductors in Standard CMOS Process,” IEEE Journal of Solid State Circuits, v. 37, no.4, April 2002, pp. 471-479.
  6. Lihui, G., Mingbin, Y. et al., “High Q Multilayer Spiral Inductor on Silicon Chip for 5~6 GHz,” IEEE Electron Device Letters, v.23, no. 8, August 2002, pp 470-472.
  7. Weisshaar, A., Lan, H., Luoh, A., “Accurate Closed-Form Expressions for the Frequency-Dependent Line Parameters of On-Chip Interconnects on Lossy Silicon Substrate,” IEEE Transactions on Advanced Packaging, v.25, no.2, May 2002, pp.288-296.
  8. Ruehli, A.E., “Inductance Calculations in a Complex Integrated Circuit Environment,” IBM J. of Research and Development, September 1972, pp. 470-481.