Title: Hierarchical Methods for Diagnostic Analysis of Digital Systems

Title: Hierarchical Methods for Diagnostic Analysis of Digital Systems

ESF Grant1850 (1996-99)

Title: Hierarchical methods for diagnostic analysis of digital systems

Principal investigator: prof. R.Ubar

Abstract: A new generalized diagnostic model for representing digital systems based on decision diagrams was developed. Based on this model, a novel multi-valued simulation method for gate-level digital ciruits was implemented [1.2,5-7]. The method allowed to generalize gate-level simulation algorithms for macros, and to increase thanks to lower complexity of the model considerably the speed of simulation. An automated mixed-level test pattern generator operating on register-transfer level (RTL) and gate-level representations of digital systems was developed [3,4,8]. The system implements a novel test generation approach based on a uniform diagnostic model of a digital system for mixed-level representations in form of decision diagrams.The approach allows to define a general fault model which uniformly covers high-level functional and low-level stuck-at fault models, and to apply standardized procedures for fault activation, fault propagation and line justification on both levels. On the basis of this approach a very fast hierarchical automated test pattern generator (ATPG) DECIDER was developed [9-10, 12-14]. For a specific class of tasks the ATPG is faster than known from literature found analogical ATPGs. Commercial ATPGs of such type are missing. A new method for single gate design error diagnosis was developed in a cooperation with TIMA Laboratory in Grenobel which is faster than a known SW tool [11].

Application: The hierarchical ATPG for digital systems DECIDER has been demonstrated in several exhibitions (CeBIT, Estonian Innovation Exhibition etc.). Since commercial SW tools for hierarchical test generation are missing, there is a possibility to find for DECIDER a wider application. Till now it has been used for testing industrial complex circuits at the Fraunhofer Institute of Integrated Circuits in Dresden (Germany), and in research experiments in cooperation with researchers from Sweden, Germany and Italy.

Publications:

  1. R.Ubar. Boolean Derivatives and Multi-Valued Simulation on Binary Decision Diagrams. 4th International Workshop on Mixed Design of Integrated Circuits and Systems. Poznan, June 12-14, 1997, pp.115-120.
  2. R.Ubar. Multi-Valued Simulation of Digital Circuits. Proc. of the IEEE21st Int. Conference on Microelectronics. Nis, Yugoslavia, September 14-17, 1997, pp. 721-724.
  3. G. Jervan, A.Markus, J.Raik, R.Ubar. Assembling Low-Level Tests to High-Level Symbolic Test Frames.IEEE 15th NORCHIP Conference, Tallinn, November 10-11, 1997, pp. 275-280.
  4. R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. Journal of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38:3, pp.317-329, 1998.
  5. R.Ubar. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams. Gordon and Breach Publishers, Multiple Valued Logic, Vol. pp. 1-17, 1998.
  6. R.Ubar. Dynamic Analysis of Digital Circuits with Multi-Valued Simulation. Microelectronics Journal, Elsevier Science Ltd., Vol. 29, No. 11, Nov. 1998, pp.821-826.
  7. R. Ubar. Dynamic Analysis of Digital Circuits with 5-valued Simulation. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, 1998, pp.187-192.
  8. M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, 1998, pp.131-136.
  9. R.Ubar. Test Generation with Structurally Synthesized BDD Models. Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.66-68.
  10. G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: A Decision Diagram Based Hierarchical Test Generation System. Proc. of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems. Szczyrk, Poland, Sept. 2-4, 1998, pp.269-273.
  11. R.Ubar, D.Borrione. Single Gate Design Error Diagnosis in Combinational Circuits. Proceedings of the Estonian Acad. of Sci. Engng, 1999, Vol. 5 , No 1, pp.3-21.
  12. J.Raik, R. Ubar. Sequential Circuit Test Generation Using Decision Diagram Models. IEEE Proc. of Design Automation and Test in Europe. Munich, March 9-12, 1999, pp. 736-740.
  13. Markus, J.Raik, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representations. Proc. of 2nd Electronic Circuits and Systems Conference. Bratislava, September 6-8, 1999, pp. 17-20.
  14. G.Jervan, P.Eles, Z.Peng, J.Raik, R.Ubar. High-Level Test Synthesis with Hierarchical Test Generation. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999, pp.291-296.
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