The Timer - Output Compare

Laboratory Short Course

The Timer - Output Compare

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Document Number: LABS12CINTRO19 /REV 1

Reading this Document

Answers provided to the Instructor assume that the reader is using Freescale HCS12C Family Student Learning Kit, and CodeWarrior development software.

This short course has been created using an adapted version of the Process Oriented Guided Inquiry Learning (POGIL) method. For more information visit

Freescale SemiconductorLABS12CINTRO19, Rev 11

Overview

The timer overflow timing resolution is somewhat coarse for many timing applications. The Output Compare hardware allows much better timing resolution and can generate time intervals to within one clock cycle. This allows us to generate waveforms and to perform other timing tasks with great precision.

Learning Objectives

In this module you will extend your knowledge of the timer by investigating the output compare features. You will see the hardware that is used and will understand what has to be initialized to use this device. You will also learn about its interrupt capabilities.

Success Criteria

At the conclusion of this module you will be able to write a program using the output compare interrupts to generate a precise waveform.

Prerequisites

Before undertaking this module you should be able to start the timer and to generate a time delay using interrupts generated by the timer overflow flag. You must also understand the operation of the interrupt system.

More Resources and Further Information

Cady, Fredrick M., Software and Hardware Engineering: Assembly and C Programming for the Freescale HCS12 Microcontroller, 2nd edition. (New York: Oxford University Press, Inc., 2008), Chapter 12 HCS12 Interrupts and Chapter 14 HCS12 Timer
CPU12 Reference Manual, S12CPUV2.PDF, Freescale Semiconductor, Inc.
TIM_16B8C Block User Guide, S12TIM16B8CV1/D.PDF, Freescale Semiconductor, Inc., October 2001.
MC9S12C Family, MC9S12GC Family Reference Manual HCS12 Microcontrollers, Freescale Semiconductor, Austin, Texas, December 2006 (mc9s12c128v1.pdf)

Timer Output CompareBasics

Figure 1 shows the hardware added to the basic timer counter. As before, the 16-bit TCNT counter is the heart of the system. The hardware added for the output compare are eight 16-bit comparators and eight 16-bit Timer Input Capture/Output Compare registers labeled TCn. (In the following, n = 0 through 7 to denote one of the eight timer channels.)
Remember that the TCNT counter is always counting (when TEN = 1). When the current value of TNCT equals the value in a TCn register, the 16-bit comparator sets the CnF flag in the TFLG1 register. This is similar to the operation of the timer overflow flag but can occur at any TCNT value, not just when the counter overflows. We can use this feature to generate accurate timing intervals.
In Figure 1 we see that CnF is ANDed with two other bits that must be asserted to allow the Output Compare Interrupt Request to be generated. The CnI bit is the Timer Interrupt Enable bit and is in the TIE register. It must be set to enable the output compare interrupt. The I bit in the Condition Code Register (CCR) is a mask bit and must be reset (= 0) to unmask the interrupt request. The CnI bit enables only this interrupt while the I bit operates globally, affecting all interrupting subsystems.
Further inspection of Figure 1 shows a Timer Input Capture/Output Compare Select Register – TIOS. Any of the eight timer channels may be chosen to be an output compare function by setting the associated bit in the TIOS register.
The CnF flag may also affect the associated Port T output bit through the Output Bit Control. This allows us to automatically change an output bit each time the output compare occurs.

Figure 1. Timer Output Compare (reprinted with permission Oxford University PressInc.). /

Teach:

The students should be able to inspect the figure and see what bits in which registers are needed to control the various features. They will be required to find in their documentation details such as register addresses and the operation of control bits.

Explore 1.

Give the addresses of the following registers:
TIE
TIOS
TC0
Which bit in the TIE register is the C0I bit and what is its state when the microcontroller is reset?

Answers:

1a) TIE = $004C
1b) TIOS = $0040
1c) TCO = $0050
2)Bit 0, reset

Stimulate 1.

Write a small section of code, either in assembly or C, that will enable timer channel 0 as an output compare.
Write a small section of code, either in assembly or C, that will enable an interrupt on timer channel 0 and then unmasks interrupts.

Answers:

1) bset TIOS,BIT0
2) bset TIE,BIT0
cli

Generating Precise Time Intervals

All time intervals are relative to some starting time and in the case of the output compare system, the starting "time" is the current value of the TCNT register. Thus, if you wish to generate an event at some time in the future, you must know two things. First, the present time is whatever value is currently in the TCNT register. You may read that with a 16-bit load instructions such as
ldd TCNT.
Second, you must convert your desired time interval to the number of TCNT clock cycles spent during this interval. When this is known, you can add this to the "present" value of the TCNT, which is in Accumulator D, with the following instruction
addd #DELAY_COUNT
and then save this future TCNT value in one of the TCn registers with
std TCn.
After making sure the CnF is reset by storing a one to the flag (just like resetting the TOF), you now have the output compare subsystem ready to set the CnF flag after the required number of TCNT clock cycles have passed.
Explore 2.
Assume the TCNT clock is 8 MHz.

What is the maximum delay one can achieve with one occurrence of an output compare?
How many clock cycles must elapse to achieve a delay of 6 milliseconds? For 1 millisecond?

Answers:

1) 8.192 ms
2) 48,000; 8,000

Stimulate 2.

The proper way to read the current value of TNCT is with a 16-bit load such as ldd TNCT. What happens if you read TCNT with two 8-bit load instructions such as

ldaa TNCT
ldab TNCT+1?

What is the worst case scenario?

Answers:

1) The TCNT counter continues to count while the ldaa instruction is executing so the ldab value will not represent the true count that existed at the first load instruction.
2) The worst case scenario is when the low byte of TCNT overflows during the first ldaa instruction.

Repeating Precise Time Intervals

Rarely would we want to delay just one time interval. Often, say when generating a square wave of some frequency, we would like repeating time delays equal to one-half the period of the square wave. After each output compare occurs, load Accumulator D from the TCn register, add the required number of clock cycles for the delay, and store that value back into the TCn. You must also reset the CnF flag by writing a one to it. At each output compare you toggle the output bit. / Common Errors: When students are asked to generate a specific frequency they calculate the period and use that for the time delay. That gives them one-half the required frequency.

Stimulate 3.

Assume you are generating a square wave of some frequency and assume the TCNT clock is 8 MHz.

What happens if instead of loading D from TCn after each output compare you load D from TCNT?
What is the lowest frequency square wave assuming the output toggles after each output compare?
What other timer feature could be used to produce the lowest frequency square wave?
What factors influence achieving the highest frequency square wave?

Answers:

1) Each delay will be extended by the number of clock cycles that have elapsed since the output compare. You end up with a lower frequency than expected.
2) 61.04 Hz
3) You could use the timer overflow.
4) The number of clock cycles needed to set up for the next output compare.

Output Compare Interrupts

Output compare interrupts are very similar to the timer overflow interrupts. By inspecting Figure 1 we see that the CnI bit must be set to enable the channel's interrupt and the I bit must be reset to unmask it.Providing the interrupt vector for this channel is initialized, the interrupt service routine will be entered when the output compare occurs. Remember to reset the CnF flag in the interrupt service routine.
Each timer channel interrupting source has a specific vector location that must be initialized with the interrupt service routine's address. In CodeWarrior this is done by the linker with the following line in the linker parameter file:
VECTOR ADDRESS 0x???? CnF_isr
or
VECTOR ?? CnF_isr
where CnF_isr is the label on your interrupt service routine and that has been XDEFed in the module where it has been defined.0x???? is the address of the vector for the timer channel in use and ?? is its priority number.
Explore 3.

In the section above, VECTORADDRESS 0x???? CnF_isr is the vector address for a timer interrupt. Where, in your documentation, do you find these addresses?
What is the vector address of Timer Channel 0?
In the section above, VECTOR ?? CnF_isr is another way of specifying that the label CnF_isr is the starting address of the timer overflow interrupt. Where, in your documentation, do you find these vector numbers?
What is the vector number of Timer Channel 0?

Answers:

1)MC9S12C Family, MC9S12GC Family Reference Manual.
2) $FFEE:FFEF
3)MC9S12C Family, MC9S12GC Family Reference Manual.
4) 8
Stimulate 4.

Inspect Figure 1and discuss what would happen in your program if your interrupt service routine did not reset the CnF?

Answers:

1) If the flag is set when returning from the interrupt service routine, an interrupt will be immediately generated and the program will return to the interrupt service routine.

Generating Long Time Intervals

A simple strategy can be followed to generate a time interval longer than the overflow time of the TCNT register. Any arbitrary time interval can be broken into a number of sub-intervals less than the TCNT overflow time. Your program can simply be set up to interrupt at these shorter times, then to count the required number in the interrupt service routine, and then change the output (or do what has to be done) when the right number of interrupts have occurred.

Output Bit Control

Look back at Figure 1. Each of the eight Port T bits may be connected to the associated timer channel to automatically change the bit each time the CnF flag is set. The bits that control this action are the OMn:OLn bits in TCTL1 and TCTL2. These bits operate in pairs to control the action on the Port T output bit (PTn).
Explore 4.

What are the addresses of TCTL1 and TCTL2?
Complete the truth table showing the action on the output bit for each of the four values of OMn:OLn.

Output Compare Result Output Action
OMn / OLn / Bit-n Action
0 / 0
0 / 1
1 / 0
1 / 1
/

Answers:

1) TCTL1 = $0048
TCTL2 = $0049
2)00 = Bit disconnected
01 = Toggle the bit
10 = Clear the bit
11 = Set the bit
Skill Exercise 1

Using the resources in your student learning kit or laboratory hardware, demonstrate to your laboratory instructor that you can use the output compare interrupts to generate a square wave with a frequency of your choice.

Communication – Inter-Group

Join another laboratory group and compare your solutions to Skill Exercise 1. Now, jointly work out changes to the design of each of your programs to produce a pulse waveform with a 25% duty cycle.

Reflection on Learning

How does your group's solution to Skill Exercise 1 compare with another group? Can you see improvements to make to your program to make it more efficient or more easily understood by somebody else?

Communication – Reporting

Demonstrate the 25% duty cycle pulse waveform.

Instructor's Notes

Output compare interrupt example

Freescale HC12-Assembler
(c) Copyright Freescale 1987-2006
Abs. Rel. Loc Obj. code Source line
------
1 1 ; This program demonstrates the
2 2 ; Timer Output Compare Interrupts.
3 3 ; The program uses the WAI instruction
4 4 ; while waiting for an interrupt.
5 5 ; The program will alternately flash LED1
6 6 ; and LED2 on a CSM-12C32
7 7 ; microcontroller module at approximately
8 8 ; 2 Hz.
9 9 ;********************************
10 10 ; Define the entry point for the main program
11 11 XDEF Entry, main
12 12 XDEF oc0_isr
13 13 XREF __SEG_END_SSTACK
14 14 ; Register equates
15 15 0000 0044 TCNT: EQU $0044 ; Timer Counter Register
16 16 0000 0046 TSCR1: EQU $0046 ; Timer System Control Register 1
17 17 0000 004D TSCR2: EQU $004d ; Timer System Control Register 2
18 18 0000 0040 TIOS: EQU $0040 ; Timer Input Capture/Output Compare Select
19 19 0000 0050 TC0: EQU $0050 ; Register 0
20 20 0000 004C TIE: EQU $004C ; Timer Interrupt Enable Register
21 21 0000 004E TFLG1: EQU $004E ; Timer Interrupt Flag Register 1
22 22 0000 0080 TEN: EQU %10000000 ; Timer enable
23 23 0000 0080 TOF: EQU %10000000 ; Timer overflow flag
24 24 0000 0000 PTA: EQU $0000 ; Port A
25 25 0000 0002 DDRA: EQU $0002 ; Data Direction
26 26 0000 0001 PTB: EQU $0001 ; Port B
27 27 0000 0003 DDRB: EQU $0003 ; Data Direction
28 28 0000 0001 BIT0: EQU %00000001 ; Bit 0
29 29 ;********************************
30 30 ; Constants
31 31 0000 0001 LED1: EQU %00000001 ; LED1 on Port A-0
32 32 0000 0010 LED2: EQU %00010000 ; LED2 on Port B-4
33 33 0000 C350 DELAY: EQU 50000 ; Clocks for each interrupt
34 34 0000 0028 COUNT: EQU 40 ; Interrupts per 1/4 sec
35 35 ; Code Section
36 36 MyCode: SECTION
37 37 Entry:
38 38 main:
39 39 000000 CFxx xx lds #__SEG_END_SSTACK
40 40 ; DO Initialize the I/O
41 41 ; Set the initial LED states
42 42 000003 4C02 01 bset DDRA,LED1 ; Make PA-0 output
43 43 000006 4C03 10 bset DDRB,LED2 ; Make PB-4 output
44 44 ; Initialize the LEDs (LEDs are active low)
45 45 000009 4C00 01 bset PTA,LED1 ; LED1 off
46 46 00000C 4D01 10 bclr PTB,LED2 ; LED2 on
47 47 ; Enable the Timer
48 48 00000F 4C46 80 bset TSCR1,TEN ; Enable the timer
49 49 ; Enable Output Compare Channel 0
50 50 000012 4C40 01 bset TIOS,BIT0
51 51 ; Grab the value of the TCNT register
52 52 000015 DC44 ldd TCNT
53 53 000017 5C50 std TC0
54 54 ; Set up the interrupts
55 55 000019 8601 ldaa #BIT0
56 56 00001B 5A4E staa TFLG1 ; Clear C0F
57 57 ; Enable OC0 interrupts
58 58 00001D 4C4C 01 bset TIE,BIT0
59 59 ; Initialize the 1/4 sec counter
60 60 000020 180B 28xx movb #COUNT,delay_count
000024 xx
61 61 ; Unmask interrupts
62 62 000025 10EF cli
63 63 ; ENDO Initialize the I/O
64 64 ; DO
65 65 main_loop:
66 66 000027 3E wai ; Wait for interrupt
67 67 ; IF the toggle flag is set
68 68 000028 1Fxx xx01 brclr toggle_flag,BIT0,end_if
00002C 15
69 69 ; THEN toggle the LEDs, clear the flag and reset counter
70 70 00002D 9600 ldaa PTA
71 71 00002F 8801 eora #LED1 ; Toggle the bit
72 72 000031 5A00 staa PTA
73 73 000033 9601 ldaa PTB
74 74 000035 8810 eora #LED2
75 75 000037 5A01 staa PTB
76 76 ; Re-initialize the delay counter
77 77 000039 180B 28xx movb #COUNT,delay_count
00003D xx
78 78 00003E 1Dxx xx01 bclr toggle_flag,BIT0 ; Clear flag
79 79 end_if:
80 80 000042 20E3 bra main_loop
81 81 ; FOREVER
82 82 ;********************************
83 83 ; Output Compare ISR
84 84 ; Decerements a "delay_counter" in memory
85 85 ; When the counter reaches zero, set a
86 86 ; toggle flag.
87 87 ;********************************
88 88 oc0_isr:
89 89 ; Decrement the counter
90 90 000044 73xx xx dec delay_count
91 91 ; IF the counter is zero
92 92 000047 2604 bne endif
93 93 ; THEN set the flag to toggle the LED
94 94 000049 1Cxx xx01 bset toggle_flag,BIT0
95 95 ; ENDIF counter is zero
96 96 endif:
97 97 ; Set up TC0 for the next time
98 98 00004D DC50 ldd TC0
99 99 00004F C3C3 50 addd #DELAY
100 100 000052 5C50 std TC0
101 101 ; Clear the flag
102 102 000054 8601 ldaa #BIT0
103 103 000056 5A4E staa TFLG1 ; Clear C0F
104 104 000058 0B rti
105 105 ;********************************
106 106 ;
107 107 Data: SECTION
108 108 000000 delay_count: DS.B 1
109 109 000001 toggle_flag: DS.B 1

Freescale SemiconductorLABS12CINTRO19, Rev 11

Revision History

Revision / Comments / Author
0 / Initial Release / Fred Cady
1 / Changed program example / Fred Cady

Freescale SemiconductorLABS12CINTRO19, Rev 11

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