The Analog section of the Front-End Board v. 2.1
(Last updated: August 1, 2001)
S.Argiro’1, D.Camin2, P.Cattaneo3, E.Menichetti1, P.Trapani1
1 University and INFN, Torino
2 University and INFN,Milano
3 INFN Pavia
1. Overview of the Front-End Board
We have developed a second version of the Analog section of the Front-End Board (FEB). For a history of earlier versions, see [i]. The Digital section, containing FADC, memories etc, has been developed by the Karlsruhe group . The original design and simulation of the channel electronics for the Analog section has been made by the Milano and Pavia groups. The physical implementation, layout and routing of the board has been made by the Torino. There has been a strong interaction between our Italian groups and the German group in Karlsruhe in all the phases of this design.
2. Design guidelines
Design guidelines for this version 2.1 have been the following:
- Have a full separation of digital and analog worlds (ground, power, signals, controls)
- Implement the Virtual Channel solution for the dynamic range expansion with respect to the FADC 12 bit capability. The Compressor solution [ii], initially implemented in version 1.0, has been found to raise some problems in terms of reliability, implementation complexity, power consumption and reconstruction of waveforms.
- Try to implement all the testing facilities and controls foreseen for a final version, in order to allow for best interconnections with the rest of the trigger and readout system
- Allow for as many programmable controls of the chain as possible, in order to facilitate setting-up and tuning
3. Description of the Analog section –version 2.1
The Analog section is a sort of daughter board of the FEB, the mother board being the Digital section. The full FEB is a 9U high, 220 mm deep Eurocard assembly, housed by a standard VME-like crate and power supply. The FEB is made by a 6U high Digital section and a 3U high Analog section, connected vertically by 3 high-density, microminiature 50-pin connectors. The Analog section is also connected to a dedicated analog backplane by one standard 96-pin connector (Fig. 1).
The board contains 22 channels of Front-End analog electronics, serving as many pixels, plus two lower gain virtual channels, meant to add up 11 channels each one. Channels are arranged into two arrays, consisting of eleven elements each one. The first array contains odd numbered channels (1 to 21), the second even ones (2 to 22). Analog differential signals from the Camera Distribution Board are received over the auxiliary (analog) backplane at the top of the rear side of the crate, 22 per connector. A list of all the board connections is shown in Appendix A .Signals are then routed through the chain, whose block diagram is shown in Fig. 2. With the two Virtual channels, the total number of differential outputs (to the FADC sitting in the Digital section) is 24.
The common signal of each differential input carries a level proportional to the average detector current, with the goal of providing a background signal useful for debugging and control. For this purpose, the common signal is splitted out of the pair and fed to a on-board, Sigma/Delta ADC. The serial output of the ADC is continuously sent to a digital interface in the Digital section.
On the Analog Board a simple circuitry that allows sending pulses to the Head Electronics is implemented. An external pulser is connected to the board either via a pin on the backplane (ATP) or through a Lemo connector located on the front panel. The signal is then routed to two differential line drivers, and sent to the Head Electronics over two twisted-pair cables (TP1OUT+, TP1OUT-,TP2OUT+, TP2OUT). These are meant to be injected at the very front-end, right before the differential line driver from the anode signal to the AB, through a transistor switch. The first twisted pair will serve channels corresponding to 1 through 11 on the AB, while the second will serve channels 12 through 22. In this way, each signal will serve half a column of PMTs on the camera. Two active-low signals, /EN_C1 and /EN_C2, perform the enabling of the drivers on the AB. They are sent out as EN_CxD to the Head Electronics to switch the transistors on. In addition, the possibility of generating test pulses on the Analog Board, without the need of an external pulser, has been foreseen. Acting on the digital lines /TP1 and /TP22 will cause an analog switch to generate a pulse swing from ground to a programmable level, named ATP. This will simulate a pulse which is routed to the differential line drivers of above. Signals /TP1 and /TP22 serve channels 12..22 and 1..11 respectively. To avoid sending signals to unwanted channels, the same /TPxx lines can be used to disable the corresponding line receivers.
A further test feature allows generation of test patterns, simulating a fluorescence light track traversing the camera, as suggested by the Karlsruhe group. Again, the /TPxx lines are used to drive analog switches from ground to a programmable level. This simulated fluorescence pulse is then injected into the line receiver reference input. The presence of the Head Electronics is therefore not required.
Chain control and setting is performed with some flexibility, upon changing the value of programmable potentiometers. A single programmable pot per channel will fix the gain of the input stage. Power consumption levels have been kept as low as possible, although a margin for improvement exists. With the present levels of power supply voltage, we anticipate a linear range of 0 : 4 V for our output signals.
3. Changes from version 1 to version 2
A summary of the most important changes from version 1.0 to version 2.1 follows:
· Implementation of the Virtual Channel solution alone for dynamic range compression
· Implementation of the Test Pattern to simulate fluorescence track in the camera without Head Electronics
· Implementation of internal test pulse generation
· Replacement of voltage regulators and substitution by LC filters
· Changes in the Antialiasing filter: from a 3-pole with cut at 1.5 MHz to a 4-pole with cut a 4.1 MHz
4. Status of the project (1/8/2001)
48 Analog Boards have been produced and delivered during the month of February. This is enough to equip two Telescopes with spares.
The boards were proven to function properly on site, a detailed performance study is ongoing.
A problem of digital noise pickup has been identified. While hoping to improve the layout to avoid the effect in the production design, we are confident that it will not harm productive prototype operation.
Figure 1 : Board Layout
Appendix A
SIGNAL DESCRIPTION:
POWER LINES:
INPUT
/Where
/Dig/An
/I
mA
/Turns
into
/I
mA
/Meaning
+V+5.2V / A27,B27,C27
On P0 / A / +Va1 / Regulated to +5V
Serves Analog Channels 1-3-5-7
+Va2 / Serves Analog Channels 9-11-13-15
+Va3 / Serves Analog Channels 17-19-21-23
+Va4 / Serves Analog Channels 2-4-6-8
+Va5 / Serves Analog Channels 10-12-14-16
+Va6 / Serves Analog Channels 18-20-22-24
-V
-5.2V / A28,B28,C28
On P0 / A / -Va1 / As above for negative polarity
-Va2
-Va3
-Va4
-Va5
-Va6
±V
±5.2V / As above / A / ±VM / Regulated to ±5V powers the two differential line drivers on sheet TPULSE
+V / As above / A / +V_SD / Regulated to +5V,powers the analog sections of the four AD73360 on sheet ADCs
+3.3V / JDH1 A18,B18, A17,B17 / D / VDD / Powers the Digital section of the AD AD73360
+5V_A / P0 A29, B29,C29 / A / +5V_A
on JDH1,
JDH2,
JDH3 / Serves the FADCs on the Digital Board
-12V / C30 on P0 / A / Used to enable the NPN transistor on the HE to allow injection of TP
DIGITAL CONTROLS
DPOT
DCS[0..3] / JDH2 A7,A8,B7,B8 / 4 in 16 decoding for Chip select of the 7 DPOTAfter decoding CS[0..6] on page DPOT Note that when no chip is selected a Null code must be
set (e.g. 1111)
PSDI, PSDO / JDH2 A9,B9 / Serial I/O for the DPOT. The chips are connected in parallel
MCLK / JDH3 A19 / MCLK (10Mhz)is sent to the DPOTS as CLK only when a chip is selected
GI[1..24] / Sheets DPOT, Channels / Connected to the terminals of the potentiometers, Gain controls
GO[1..24] / As Above
/TP1..22 / JDH1, JDH2, JDH3 / Test Pulse and Test Pattern controls
VBIAS[1..2] / DPOT, ADCs / allows biasing the reference to the AD73360
ADCs (AD73360)
SDIFS, SDOFS / A22,B22 / Frame sync signals for operation of the Ad73360 Serial PortSDI, SDO / JDH3 A21,b21 / Serial Data I/O
SE / JDH3 A20 / Serial Port Enable
RESET / JDH3 B20 / Reset
MCLK / JDH3 A19 / Master Clock (10Mhz)
SCLK / JDH3 B19 / Serial Port clock (out from ad73360, made from MCLK divided by some programmable ratio)
GREF1,GREF2 / JDH3 A12, A25 on P0 / Ground reference (shield) for inputs 1-11 and 12-22
VBIAS[1..2] / see DPOT
TPULSE
TP_IN / Front panel orATP (A30 on P0) / Test Pulse In
/EN_C1, /EN_C2 / JDH2 B6, JDH3 B15 / Active low, enables test pulsing on channels 1-11 or 12-22
EN_C1D, EN_C2D / P0 C12, C25 / 0 or -12V to enable test pulsing on the Head
TP1OUT+, TP1OUT-
TP2OUT+, TP2OUT- / A13, A26, C13, C26 on P0 / Test Pulse Out to HE
on two twisted-pairs
ANALOG Channels
+V[1..22] / P0 A1-A11, C1-C11 / Differential input-V[1..22] / P0 A14-A24, C14-C24
VOUT[1..22] / JDH 1,2,3 / output signal
SGND[1..24] / output signal ground reference
VOUT23 / JDH 2 / virtual channel :
sum of odd channels
VOUT24 / JDH 3 / virtual channel: sum of even channels
Connector J1 / Connector J2 / Connector J3
Pin #
/row a
/row b
/row a
/row b
/row a
/row b
1 / SGnd01 / Vout01 / SGnd21 / Vout21 / Vout14 / SGnd142 / AGND / AGND / AGND / AGND / AGND / AGND
3 / Vout03 / SGnd03 / Vout23 / SGnd23 / SGnd16 / Vout16
4 / +5V_A / AGND / AGND / AGND / +5V_A / AGND
5 / SGnd05 / Vout05 / Spare_1 / Spare_2 / Vout18 / SGnd18
6 / AGND / AGND / /Tp21 / En_C1 / AGND / AGND
7 / Vout07 / SGnd07 / DCS2 / DCS3 / SGnd20 / Vout20
8 / +5V_A / AGND / DCS0 / DCS1 / +5V_A / AGND
9 / SGnd09 / Vout09 / PSDI / PSDO / Vout22 / SGnd22
10 / AGND / AGND / VDD / DGND / AGND / AGND
11 / Vout11 / SGnd11 / /Tp02 / /Tp04 / SGnd24 / Vout24
12 / +5V_A / AGND / /Tp06 / /Tp08 / AGND / AGND
13 / SGnd13 / Vout13 / /Tp10 / /Tp12 / /Tp14 / /Tp16
14 / AGND / AGND / AGND / AGND / /Tp18 / /Tp20
15 / Vout15 / SGnd15 / Vout02 / SGnd02 / /Tp22 / En_C2
16 / +5V_A / AGND / +5V_A / AGND / DGND / DGND
17 / SGnd17 / Vout17 / SGnd04 / Vout04 / VDD / VDD
18 / AGND / AGND / AGND / AGND / +5Vdig / +5Vdig
19 / Vout19 / SGnd19 / Vout06 / SGnd06 / MCLK / SCLK
20 / +5V_A / AGND / +5V_A / AGND / SE / RESET
21 / /Tp01 / /Tp03 / SGnd08 / Vout08 / SDI / SDO
22 / /Tp05 / /Tp07 / AGND / AGND / SDIFS. / SDOFS
23 / /Tp09 / /Tp11 / Vout10 / SGnd10 / Pos0 / Pos1
24 / /Tp13 / /Tp15 / +5V_A / AGND / Pos2 / Pos3
25 / /Tp17 / /Tp19 / SGnd12 / Vout12 / Pos4 / PosRef
Spare_1 and Spare_2 are connected to the FPGA (function to be defined later)
Pin # Row A Row B Row C Function Specification:
1 V+1 AGnd V-1 Differential Input of PMT #1, 5V pp, +/-2.5V relative to GRef1
2 V+2 AGnd V-2 Differential Input of PMT #2, 5V pp, +/-2.5V relative to GRef1
3 V+3 AGnd V-3 ......
4 V+4 AGnd V-4 ......
5 V+5 AGnd V-5 ......
6 V+6 AGnd V-6 ......
7 V+7 AGnd V-7 ......
8 V+8 AGnd V-8 ......
9 V+9 AGnd V-9 ......
10 V+10 AGnd V-10 Differential Input of PMT #10, 5V pp, +/-2.5V relative to GRef1
11 V+11 AGnd V-11 Differential Input of PMT #11, 5V pp, +/-2.5V relative to GRef1
12 GRef1 AGnd En_C1D Reference for CM chn 1..11 and testpulse enable
13 TP1O+ AGnd Tp1O- Differential testpulse for chn 1..11 at HE
14 V+12 AGnd V-12 Differential Input of PMT #12, 5V pp, +/-2.5V relative to GRef2
15 V+13 AGnd V-13 Differential Input of V+T #13, 5V pp, +/-2.5V relative to GRef2
16 V+14 AGnd V-14 ......
17 V+15 AGnd V-15 ....
18 V+16 AGnd V-16 ......
19 V+17 AGnd V-17 ......
20 V+18 AGnd V-18 ......
21 V+19 AGnd V-19 ......
22 V+20 AGnd V-20 ......
23 V+21 AGnd V-21 Differential Input of PMT #21, 5V pp, +/-2.5V relative to GRef2
24 V+22 AGnd V-22 Differential Input of PMT #22, 5V pp, +/-2.5V relative to GRef2
25 GRef2 AGnd En_C2D Reference for CM chn 12..22 and testpulse enable
26 TP2O+ AGnd TP2O- Differential testpuls for chn 12..22 at HE
27 +V1 +V2 +V3 +V[1..3]: positive analog supply voltage (to be defined +5..+12 V ) total current per slot: < 500 mA
28 -V1 -V2 -V3 -V[1..3]: negative analog supply voltage (to be defined –5..-12 V ) total current per slot: < 500 mA
29 +5V_A +5V_A +5V_A analog +5V for ADCs and sigma/delta; -12V for testpulser total current per slot: < 1000 mA