Supplemental Documentation
Critical Path Delay
The input transition is A<0> = 0 to 1, A<1:15>=0, B<0:15> = 1 for this simulation. This produces the worst case delay in the ALU. At the second rising clock, A0 gets registered and takes a long time to rise due to the huge capacitance that it has to drive. The capacitances are contributed by all the operations in out ALU except for the multiplier, which was disabled. Due to this slow rise in A0, the output of the ALU takes a long to recognize the input change. With all these factors, the delay from the second rising clock edge to OutALU15 is 18.33949 ns.
Power Simulation
The first figure displays the requested inputs and outputs to be graphed. The first column represents Ain bits from 9 to 6. The second column represents Bin bits from 9 to 6. The third column represents the ALUOut bits from 9 to 6, and the fourth column represents the output bits from 9 to 6, with the carry out being represented as the very last graph. Due to the scaling of the image, it may be hard to see the scaling of the axes. All of the y-axes go from –1V to 6V, while the x-axes go from 0 to 800ns.
The second figure details the power consumption of the ALU block when simulated with the specified values. The first section of the graph shows the current consumed by the ALU during the simulation. From this, you see that the current going through is a negative current, thus it is current being consumed by the ALU. The second section of this graph plots the value of the ALU's voltage source. This source remains at +5V throughout. The third portion of the graph shows the clock that is driving this circuit. The last section of the graph shows the power being consumed by the ALU. This is shown by multiplying the voltage through the ALU by the current being consumed by the ALU. The Energy is 1.248221e-8 J, and the power we have calculated is the average value of this graph, which we have calculated to be .0156 W.
. Arbitrary Function Simulation
The inputs A and B to for the multiplier were 11000000 => 192. The result should change only the 15th bit and the 12th bit from 0 to 1. The rest of the outputs should remain 0s. The delay was calculated from the rising edge of the clock to the rising edge of the 15th bit and was measured to be around 0.492ns.
List of Subcircuits
// Subcircuits for use in the AMI06 technology
simulator lang=spectre
//------LAST MODIFIED 4/26/10------//
/*
1) our wiki things
-2:1MUX = ece3663MUX2to1
-4:1MUX = ece3663MUX4to1
-TGATE = ece3663tgate
-TGATE MUX = ece3663tGateMux
2) class wiki things
-Inverter = ece3663Inverter
-2 input NAND = ece3663NAND2
-2 input NOR = ece3663NOR2
-2 input AND = ece3663AND2
-2 input OR = ece3663OR2
-2 input XOR = ece3663XOR2
-2 input XNOR = ece3663XNOR2
-3 input NAND = ece3663NAND3
-3 input NOR = ece3663NOR3
-3 input AND = ece3663AND3
-3 input OR = ece3663OR3
-F1 = (AB + BC + AC)' = ece3663F1
-F2=(A*B*C+D*(A+B+C))' = ece3663F2
3) things to make our lives easier
-buffer
-MUX8to1
OUR ALU STUFF - 16b
4) register
-posDLatch
-posEdgeRegister
-registor16b
5) adder
-HalfAdder1b
-FullAdder1b
-FullAdder8b
-FullAdder16b
6) subtract=sub_16b
7) AND=and16b
8) OR =or16b
9) Transmission Gate - used instead of pass gate
-tgate16b
10) No OP = backToBackInverter (I have a feeling it's not necessary.)
11) Multiplier
-AndRow
-AdderRow1
-AdderRow2
-Multiplier8
12) Arithmetic Logic Unit
-MUX8_1_17b
-ALU
-DSP
13) leftShift
INCOMPLETE: SHIFTER = leftShift
*/
//------WIKI-STUFF----FOLLOW CLASS NAMING CONVENTIONS------1------//
// Cell name: ece3663MUX2to1
// Modified by: Team NAND
// improvement: resized NMOS transistors to reduce transmission delay
// 4/23/10 - conformed to class naming convention
// - fixed sizing mistakes for area and perimeter for NMOS
subckt ece3663MUX2to1 VDD VSS in0 in1 Select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS Select selectBar) ece3663Inverter wn=wn wp=wp mult=mult
P5 (net15 Select VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P4 (net15 in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P3 (out net15 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P2 (out net31 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P1 (net31 in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P0 (net31 selectBar VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N5 (net35 net15 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N4 (out net31 net35 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N3 (net43 Select VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N2 (net15 in1 net43 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N1 (net31 selectBar net55 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N0 (net55 in0 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
ends ece3663MUX2to1
//end subcircuit definition
//Cell name: ece3663MUX4to1
// Modified by: Team NAND
// fixed ability to size mux with variables
// 4/23/10 - conformed to class naming convention
subckt ece3663MUX4to1 VDD VSS in00 in01 in10 in11 Select0 Select1 out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS in00 in01 Select0 net75) ece3663MUX2to1 wn=wn wp=wp mult=mult
I1 (VDD VSS in10 in11 Select0 net79) ece3663MUX2to1 wn=wn wp=wp mult=mult
I2 (VDD VSS net75 net79 Select1 out) ece3663MUX2to1 wn=wn wp=wp mult=mult
ends ece3663MUX4to1
//end subcircuit definition
// Cell name: ece3663tgate
// Modified by: Team NAND
// Added ability to control the size of tgate with variables wn and wp.
// 4/23/10 - conformed to class naming convention
// - fixed wp and wn sizing mistakes
subckt ece3663tgate VDD VSS in pass out
parameters wp=3u wn =1.5u ln=600n lp=600n mult=1
I3 (VDD VSS pass pass_inv) ece3663Inverter wn=wn wp=wp mult=mult
N0 (in pass out VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
P0 (out pass_inv in VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
ends ece3663tgate
//end of subcircuit definition
// Cell: ece3663tGateMux
// Modified by: Team NAND
// added ability to control sizing from variables wn and wp.
// 4/23/10 - conformed to class naming convention
subckt ece3663tGateMux VDD VSS in0 in1 select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS in0 selectPrime out) ece3663tgate wn=wn wp=wp mult=mult
I1 (VDD VSS in1 select out) ece3663tgate wn=wn wp=wp mult=mult
I2 (VDD VSS select selectPrime) ece3663Inverter wn=wn wp=wp mult=mult
ends ece3663tGateMux
//end of subcircuit definition
//======END OUR WIKI======
//------OTHER PPLS WIKI------2----
// Cell name: ece3663Inverter
// An inverter with sizing parameters and parameterized AD,AS,PD,PS
// The S/D parameters assume a single-finger device
subckt ece3663Inverter VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
MP (out in VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MN (out in VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ece3663Inverter
// End of subcircuit definition
// Cell name: ece3663NAND2
// modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances
subckt ece3663NAND2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P1 (Out InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P0 (Out InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N1 (net18 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn \
pd=3u+2*wn m=mult
N0 (Out InA net18 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663NAND2
// End of subcircuit definition.
// Cell name: ece3663NOR2
// Modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances
subckt ece3663NOR2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P1 (Out InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult
P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult
N1 (Out InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult
N0 (Out InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult
ends ece3663NOR2
// End of subcircuit definition.
// Cell name: ece3663AND2
// Implementation: NAND in series w/ inverter
// Modified 3/17/2010 by Team Mux to correct faults in netlist parameters
// Modified 4/4/2010 by Team Mux to conform to class conventions
subckt ece3663AND2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P2 (Out net049 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
P1 (net049 InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
P0 (net049 InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
N2 (Out net049 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N1 (net22 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult region=sat
N0 (net049 InA net22 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn \
ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult region=sat
ends ece3663AND2
//end of subcircuit defn.
// Cell name: ece3663OR2
// Implementation: NOR in series with inverter
// Modified 3/17/2010 by Team MUX to standardize transistor names
// Modified 3/31/2010 by Team XOR to fix naming convention and size for equal PUN/PDN resistances
// Modified 4/4/2010 by Team MUX to fix wrong bulk connection and conform to class conventions
subckt ece3663OR2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P2 (Out net21 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
P1 (net21 InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult region=sat
P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult region=sat
N2 (Out net21 Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N1 (net21 InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N0 (net21 InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
ends ece3663OR2
//end subcircuit
// Cell name: ece3663XOR2
// An implementation of a two input XOR =A'*B+A*B'=((A'*B)'*(A*B')')'
// Inputs to the XOR are named "A" and "B"
// Output of the XOR is named "out"
// High voltage is named "VDD"
// Low voltage (ground) is named "VSS"
//subsubcircuit inverters used have been sized to make worst-case PUN resistance and worst-case PDN resistance the same
//subsubcircuit NANDs used have been sized to make worst-case PUN resistance and worst-case PDN resistance the same
//edited by Team ADD at 10:38 p.m. on Sunday, 4 April 2010
subckt ece3663XOR2 VDD VSS A B out
parameters wpGlobal=3u wnGlobal=1.5u lnGlobal=600n lpGlobal=600n multGlobal=1
//subsubcircuits that invert the inputs
//inverter for input A
invA (VDD VSS A notA) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal mult=multGlobal
//inverter for input B
invB (VDD VSS B notB) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal mult=multGlobal
//basically first input NAND
p1comma1 (intermediate1 notA VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
p1comma2 (intermediate1 B VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
n1comma1 (intermediate1 notA node1 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n1comma2 (node1 B VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
//basically second input NAND
p2comma1 (intermediate2 A VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
p2comma2 (intermediate2 notB VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
n2comma1 (intermediate2 A node2 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n2comma2 (node2 notB VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
//basically third combining/output NAND
p3comma1 (out intermediate1 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
p3comma2 (out intermediate2 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
n3comma1 (out intermediate1 node3 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n3comma2 (node3 intermediate2 VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
ends ece3663XOR2
// End of subcircuit definition
// Cell Name: ece3663XNOR2
// Edited by Team XOR: a 2-input XNOR gate built from other subcircuits
// Has tunable parameters including: wp, wn, lp, ln, and m
// Has parameterized AS, AD, PS, PD
// Implements the function: XNOR = ((F*G)')'
// where F = B + A'B' and G = A + A'B'
// not the most efficient implementation, but this is what the 2008 group chose to do.
// originally this was made of 18 discrete transistors with a ridiculous netlist that was
// very difficult to understand. we've improved this by "packaging" the transistors into
// the gates they had essentially created.
subckt ece3663XNOR2 (VDD VSS A B Out)
parameters wp=3u wn=1.5u lp=600n ln=600n mult=1
NOR (VDD VSS A B center) ece3663NOR2 wp=wp wn=wn lp=lp ln=ln mult=mult
ORtop (VDD VSS B center F) ece3663OR2 wp=wp wn=wn lp=lp ln=ln mult=mult
ORbottom (VDD VSS A center G) ece3663OR2 wp=wp wn=wn lp=lp ln=ln mult=mult
NAND (VDD VSS F G Outbar) ece3663NAND2 wp=wp wn=wn lp=lp ln=ln mult=mult
INVERTER (VDD VSS Outbar Out) ece3663Inverter wp=wp wn=wn lp=lp ln=ln mult=mult
ends ece3663XNOR2
//end of subcircuit defn.
// Cell name: NAND3
// View name: schematic
// Edited by group NOR: 3 input NAND gate with tunable wp, wn, lp, ln, and m
// Sized for equal pull-up, pull-down to Inv
subckt ece3663NAND3 (VDD VSS A B C OUT)
parameters wp=3u wn=4.5u ln=600n lp=600n mult=1
MNC (NETCB C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MNB (NETBA B NETCB VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MNA (OUT A NETBA VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MPC (OUT C VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
MPB (OUT B VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
MPA (OUT A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
ends ece3663NAND3
//END OF subcircuit definition
// Cell name: NOR3
// View name: schematic
// Edited by group NOR: 3 input NOR gate with tunable wp, wn, lp, ln, and m
// Sized for equal pull-up, pull-down to Inv
subckt ece3663NOR3 (VDD VSS A B C out)
parameters wp=9u wn=1.5u ln=600n lp=600n mult=1
MPa (netab A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MPb (netbc B netab VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MPc (out C netbc VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MNa (out A VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
MNb (out B VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
MNc (out C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ece3663NOR3
// End of subcircuit definition.
// Cell name: AND3
// View name: schematic
// Edited by group NOR: 3 input AND gate with tunable wp, wn, and m
// sized for pull-up/pull-down equal to inverter
subckt ece3663AND3 (VDD VSS A B C OUT)
parameters wpA=3u wnA=1.5u multA=1
NAND (VDD VSS A B C Invertin) ece3663NAND3 wp=wpA wn=wnA*3 mult=multA
Inv (VDD VSS Invertin OUT) ece3663Inverter wp=wpA wn=wnA mult=multA
ends ece3663AND3
//end of subcircuit definition
// Cell name: OR3
// View name: schematic
// Edited by group NOR: 3 input OR gate with tunable wp, wn, and m
// sized for pull-up/pull-down equal to inverter
subckt ece3663OR3 (VDD VSS A B C out)
parameters wpO=3u wnO=1.5u multO=1
NOR (VDD VSS A B C Invertin) ece3663NOR3 wp=wpO*3 wn=wpO mult=multO
Inv (VDD VSS Invertin out) ece3663Inverter wp=wpO wn=wnO mult=multO
ends ece3663OR3
//end of subcircuit definition
// Cell name: ece3663F1
// This circuit implements the function F1 = (AB + BC + AC)'
// It has sizing parameters and parameterized AD, AS, PD, PS.
// Edited by Team XOR; we improved the circuit from 2008 by removing
// two transistors. The old implementation had 12 transistors while
// this implementation only uses 10 transistors. We were able to
// remove one transistor for both the PUN and PDN by simplifying the F1 equation to F1=(A(B+C)+BC)'
// We also sized the implementation to have equal pull-up and pull-down networks.
subckt ece3663F1 Vdd Vss A B C Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P0 (Out B Node2 Vdd) ami06P w=1.5*wp l=lp as=1.5u*1.5*wp ad=1.5u*1.5*wp \
ps=3u+1.5*wp pd=3u+1.5*wp m=mult
P2 (Node2 C Node1 Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
P3 (Node1 B Vdd Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
P1 (Out C Node2 Vdd) ami06P w=1.5*wp l=lp as=1.5u*1.5*wp ad=1.5u*1.5*wp \
ps=3u+1.5*wp pd=3u+1.5*wp m=mult
P4 (Node2 A Vdd Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
N4 (Out C Node4 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N3 (Node4 B Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N2 (Out C Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N1 (Out B Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N0 (Node3 A Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663F1
//Ends subcircuit definition
// Cell name: ece3663F2
// An implementation of the function F2=(A*B*C+D*(A+B+C))'
// Inputs to this gate are named "A", "B", "C", "D"
// Outout of this gate is named "out"
// High voltage is named "VDD"
// Low voltage (ground) is named "VSS"
// subcircuit has been sized to make the worst-case PUN resistance and the worst-case PDN resistance the same
//edited by Team ADD at 11:22 p.m. on Sunday, 4 April 2010
subckt ece3663F2 VDD VSS A B C D out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
//A in parallel with B in parallel with C in PUN
pAparallel (node1 A VDD VDD) ami06P w=(4.0/3.0)*wp l=lp as=1.5u*(4.0/3.0)*wp ad=1.5u*(4.0/3.0)*wp ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp m=mult
pBparallel (node1 B VDD VDD) ami06P w=(4.0/3.0)*wp l=lp as=1.5u*(4.0/3.0)*wp ad=1.5u*(4.0/3.0)*wp ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp m=mult
pCparallel (node1 C VDD VDD) ami06P w=(4.0/3.0)*wp l=lp as=1.5u*(4.0/3.0)*wp ad=1.5u*(4.0/3.0)*wp ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp m=mult
//D in parallel with (A in series with B in series with C) in PUN
pD (out D node1 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp m=mult
pAseries (node2 A node1 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp m=mult
pBseries (node3 B node2 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp m=mult
pCseries (out C node3 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp m=mult
//A in series with B in series with C in PDN
nAseries (out A node4 VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
nBseries (node4 B node5 VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
nCseries (node5 C VSS VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
//D in series with (A in parallel with B in parallel with C) in PDN
nD (out D node6 VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
nAparallel (node6 A VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
nBparallel (node6 B VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
nCparallel (node6 C VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663F2
// End of subcircuit definition
//======END WIKI STUFF======
//------THINGS TO MAKE OUR LIVES EASIER------3----
// Cell name: buffer
// two inverters in series
subckt buffer VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I1 (VDD VSS in i1) ece3663Inverter wp=wp wn=wn mult=mult
I2 (VDD VSS i1 out) ece3663Inverter wp=wp wn=wn mult=mult
ends buffer
// End of subcircuit definition
// Cell name: 16b Buffer
subckt buffer_16 Vdd Vss \
i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 \
o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (Vdd Vss i0 o0) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I1 (Vdd Vss i1 o1) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I2 (Vdd Vss i2 o2) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I3 (Vdd Vss i3 o3) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I4 (Vdd Vss i4 o4) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I5 (Vdd Vss i5 o5) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I6 (Vdd Vss i6 o6) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I7 (Vdd Vss i7 o7) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I8 (Vdd Vss i8 o8) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I9 (Vdd Vss i9 o9) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I10 (Vdd Vss i10 o10) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I11 (Vdd Vss i11 o11) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I12 (Vdd Vss i12 o12) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I13 (Vdd Vss i13 o13) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I14 (Vdd Vss i14 o14) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I15 (Vdd Vss i15 o15) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
ends buffer_16
// Cell name: MUX8to1
subckt MUX8to1 Vdd Vss in0 in1 in2 in3 in4 in5 in6 in7 sel0 sel1 sel2 out
parameters wn=1.5u wp=3u
M6 (Vdd Vss mux4 mux5 sel2 out) ece3663tGateMux wn=wn wp=wp
M5 (Vdd Vss mux2 mux3 sel1 mux5) ece3663tGateMux wn=wn wp=wp
M4 (Vdd Vss mux0 mux1 sel1 mux4) ece3663tGateMux wn=wn wp=wp
M3 (Vdd Vss in6 in7 sel0 mux3) ece3663tGateMux wn=wn wp=wp
M2 (Vdd Vss in4 in5 sel0 mux2) ece3663tGateMux wn=wn wp=wp
M1 (Vdd Vss in2 in3 sel0 mux1) ece3663tGateMux wn=wn wp=wp
M0 (Vdd Vss in0 in1 sel0 mux0) ece3663tGateMux wn=wn wp=wp
ends MUX8to1
//======END=THINGS TO MAKE OUR LIVES EASIER======
//------REGISTER------4------
// Cell: posDLatch
// transparent when clk level is high.
subckt posDLatch VDD VSS CLK CLKbar D Q Qbar
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P0 (link0 CLKbar D VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N0 (D CLK link0 VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
P1 (Q CLK link0 VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N1 (link0 CLKbar Q VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
I0 (VDD VSS Qbar Q) ece3663Inverter wn=wn wp=wp mult=mult
I1 (VDD VSS link0 Qbar) ece3663Inverter wn=wn wp=wp mult=mult
ends posDLatch
//end of subcircuit definition
//Cell: posEdgeRegister
// This circuit acts as a master-slave positive edge-triggered register
// - two different D-latches combined to create this register
// Q - output of the posEdgeRegister (which is the inverted output of the PosLvlLatch)
subckt posEdgeRegister VDD VSS CLK D Q
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Iclk (VDD VSS CLK CLKbar) ece3663Inverter wn=wn wp=wp mult=mult
//The clock is inverted to produce a negative level latch.
NegLevelLatch (VDD VSS CLKbar CLK D q1 q1bar) posDLatch wn=wn wp=wp mult=mult
PD1 (VDD VSS CLK CLKbar q1bar Qbar Q) posDLatch wn=wn wp=wp mult=mult
ends posEdgeRegister
//end of subcircuit definition
// Cell name: 16bitRegister
subckt register16bit vdd vss CLK d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0
parameters wp=3u wn=1.5u
I0 (vdd vss CLK d0 q0) posEdgeRegister wn=wn wp=wp
I1 (vdd vss CLK d1 q1) posEdgeRegister wn=wn wp=wp
I2 (vdd vss CLK d2 q2) posEdgeRegister wn=wn wp=wp
I3 (vdd vss CLK d3 q3) posEdgeRegister wn=wn wp=wp
I4 (vdd vss CLK d4 q4) posEdgeRegister wn=wn wp=wp
I5 (vdd vss CLK d5 q5) posEdgeRegister wn=wn wp=wp
I6 (vdd vss CLK d6 q6) posEdgeRegister wn=wn wp=wp
I7 (vdd vss CLK d7 q7) posEdgeRegister wn=wn wp=wp
I8 (vdd vss CLK d8 q8) posEdgeRegister wn=wn wp=wp
I9 (vdd vss CLK d9 q9) posEdgeRegister wn=wn wp=wp
I10 (vdd vss CLK d10 q10) posEdgeRegister wn=wn wp=wp
I11 (vdd vss CLK d11 q11) posEdgeRegister wn=wn wp=wp
I12 (vdd vss CLK d12 q12) posEdgeRegister wn=wn wp=wp
I13 (vdd vss CLK d13 q13) posEdgeRegister wn=wn wp=wp
I14 (vdd vss CLK d14 q14) posEdgeRegister wn=wn wp=wp
I15 (vdd vss CLK d15 q15) posEdgeRegister wn=wn wp=wp
ends register16bit
//end of subckt defn.
//======END REGISTER======
//------ADDER------5------
// Cell Name: HalfAdder1b
subckt HalfAdder1b Vdd Vss InA InB SOut COut
parameters wn=1.5n wp=3n
OR1 (Vdd Vss InA InB orOut) ece3663OR2 wn=wn wp=wp
AND1 (Vdd Vss InA InB COut) ece3663AND2 wn=wn wp=wp
INV1 (Vdd Vss COut invOut) ece3663Inverter wn=wn wp=wp
AND2 (Vdd Vss orOut invOut SOut) ece3663AND2 wn=wn wp=wp
ends HalfAdder1b
//end of subcircuit definition
// Cell name: FullAdder1b - Mirror Adder implementation
// Note: be aware that the wp=1.5u because the 1bit adder has been sized properly internally
subckt FullAdder1b VDD VSS INa INb cin Co Sum
parameters wp=1.5u wn=1.5u ln=600n lp=600n mult=1
P0 (link0 INa VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P1 (link0 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P2 (coutBar cin link0 VDD) ami06P w=wp*2 l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+wp*2 \
pd=3u+wp*2 m=mult
P3 (link1 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P4 (coutBar INa link1 VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P5 (sumBar coutBar link4 VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp \
ps=3u+wp*4 pd=3u+wp*4 m=mult
P6 (link4 INa VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P7 (link4 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P8 (link4 cin VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P9 (link5 INa VDD VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
P10 (link6 INb link5 VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
P11 (sumBar cin link6 VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
N0 (link2 INa VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N1 (link2 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N2 (coutBar cin link2 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N3 (link3 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N4 (coutBar INa link3 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N5 (sumBar coutBar link7 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2\
pd=3u+wn*2 m=mult
N6 (link7 INa VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N7 (link7 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N8 (link7 cin VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N9 (link8 INa VSS VSS) ami06N w=wn*3 l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+wn*3 \
pd=3u+wn*3 m=mult
N10 (link9 INb link8 VSS) ami06N w=wn*3 l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+wn*3 \