DOC/LP/01/28.02.02

/ LESSON PLAN / LP – EC2354
LP Rev. No: 02
Date: 24/12/12
Page 01 of 06
Sub Code & Name: EC2354 VLSI DESIGN
Unit : V Branch : EC Semester: VI

UNIT V SPECIFICATION USING VERILOG HDL 9

Syllabus:

Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls,procedural assignments conditional statements, Data flow and RTL, structural gate level,switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches,Structural gate level description of decoder, equality detector, comparator, priorityencoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.

Objective: To understand the concepts of modeling a digital system using Hardware Description Language.

Session No. / Topics to be covered / Time / Page No / Ref / Teaching
Method
Basic concepts- identifiers- gate primitives,Design hierarchies / 50m / 47-48,72,106,388 / 8,2 / BB
Gate delays / 50m / 121 / 8 / BB
Operators / 50m / 138 / 8 / BB
Chip Timing controls / 50m / 171-178 / 8 / BB
Procedural assignments ,conditional statements / 50m / 166,179 / 8 / BB
Data flow and RTL / 50m / 131 / 8 / BB
Structural gate level / 50m / 373 / 8 / BB
Switch level modeling / 50m / 383 / 8 / BB
Behavioral and RTL modeling, Test benches / 50m / 385 / 8 / BB
Gate level verilog code-Decoder, equality detector, comparator, priorityencoder / 50m / 136 / 8 / BB
Half adder, full adder, Ripple carry adder, D latch and D flip flop. / 50m / 452,414 / 2,4 / BB
/ LESSON PLAN / LP – EC2354
LP Rev. No: 02
Date: 24/12/12
Page 02 of 06
Sub Code & Name: EC2354 VLSI DESIGN
Unit : I Branch : EC Semester: VI

DOC/LP/01/28.02.02

UNIT I CMOS TECHNOLOGY 9

Syllabus:

A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I-Veffects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOSprocess enhancements, Technology related CAD issues, Manufacturing issues.

Objective: To understand the MOS transistor theory,CMOS technologies and the Layout.

Session No. / Topics to be covered / Time / Page No / Ref / Teaching Method
Introduction –VLSI Design / 50m / 1-4 / 1 / BB
NMOS, PMOS Enhancement transistor / 50m / 5-7,40 / 1 / BB
MOS transistor-Ideal I-V characteristics / 50m / 42-45 / 1 / BB
MOS transistor-C-V characteristics / 50m / 45-51 / 1 / BB
Nonideal I-V characteristics- velocity saturation and mobility degradation, channel length modulation, subthreshold conduction / 50m / 51-55 / 1 / BB
Threshold voltage, Body effect, Junction leakage, Tunneling, temperature dependence, Geometry dependence / 50m / 55-60 / 1 / BB
CMOS inverter DC characteristics, Beta ratio effects / 100m / 60-65 / 1 / BB
CMOS technology : n well, p well Twin well, triple well, / 50m / 83,
15-21 / 1,3 / BB
Layout design rules-NAND,NOR gat / 50m / 83-91 / 1 / BB
CMOS Process enhancement-SOI Process, Interconnects, circuit elements: Resistors, / 50m / 91-100 / 1 / BB
Circuit element: capacitor, CAD and manufacturing issues / 50m / 107-109,149 / 1,2 / BB

DOC/LP/01/28.02.02

/ LESSON PLAN / LP – EC2354
LP Rev. No: 02
Date: 24/12/12
Page 03 of 06
Sub Code & Name: EC2354 VLSI DESIGN
Unit : III Branch : EC Semester: VI

UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9 9

Syllabus:

Circuit families –Low power logic design – comparison of circuit families – Sequencing static circuits, circuit design of latches and flip flops, Static sequencing elementmethodology- sequencing dynamic circuits – synchronizers

Objective: To understand the concepts of designing combinational and sequential circuit using CMOS logic configuration

Session No. / Topics to be covered / Time / Page No / Ref / Teaching Method
Circuit families-static CMOS,ratioed circuit / 50m / 215-224,342 / 1,2 / BB
Cascode voltage swing logic,Dynamic circuits / 50m / 225,361,
353 / 1,2,3 / BB
Pass transistor,Differential circuits / 50m / 233-240 / 1 / BB
BiCMOS,Low power logic design – comparison of circuit families / 50m / 241-245 / 1 / BB
Sequencing static circuits / 50m / 252-265 / 1 / BB
Circuit design of latches and flip flops / 50m / 265-274 / 1 / BB
Static sequencing element / 50m / 275-283 / 1 / BB
Sequencing dynamic circuits / 50m / 284-289 / 1 / BB
Synchronizers / 50m / 289-294 / 1 / BB

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/ LESSON PLAN / LP – EC2354
LP Rev. No: 02
Date: 24/12/12
Page 04 of 06
Sub Code & Name: EC2354 VLSI DESIGN
Unit : IV Branch : EC Semester: VI

UNIT IV CMOS TESTING 9

Syllabus:

Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicondebug principles- Manufacturing test – Design for testability – Boundary scan.

Objective:To understand the concepts of CMOS testing

Session No. / Topics to be covered / Time / Page No / Ref / Teaching Method
Need for testing / 50m / 531-536 / 1 / BB
Text fixtures and test programs / 50m / 537-540 / 1 / BB
Logic verification- Silicon
debug principle / 50m / 541-544 / 1 / BB
Manufacturing test / 50m / 544,621,239 / 1,2,4 / BB
------do ------/ 50m / 544,621,239 / 1,2,4 / BB
Design for testability-adhoc testing / 50m / 548-550 / 1 / BB
Scan design / 50m / 550-555 / 1 / BB
Built in self test, IDDQ testing / 50m / 555-558 / 1 / BB
Boundary scan / 50m / 559-570 / 1 / BB
CAT I / 180m / - / - / -

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/ LESSON PLAN / LP – EC2354
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Date: 24/12/12
Page 05 of 06
Sub Code & Name: EC2354 VLSI DESIGN
Unit : II Branch : EC Semester: VI

UNIT IICIRCUIT CHARACTERIZATION AND SIMULATION 9

Syllabus:

Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Devicecharacterization, Circuit characterization, Interconnect simulation.

Objective:To study the circuit characterization and performance estimation of CMOS technology .

Session No. / Topics to be covered / Time / Page No / Ref / Teaching Method
41 / Delay estimation-RC delay model,Linear delay model / 50m / 111-117,245 / 1,2 / BB
42 / Logical effort / 50m / 118,313 / 1,2 / BB
43 / Transistor sizing / 50m / 118 / 1 / BB
44 / Power dissipation-static and dynamic power / 50m / 129-135 / 1 / BB
45 / Interconnect –Estimation of resistance capacitance, delay and cross talk / 50m / 135-145,525 / 1,2 / BB
46 / Design margin / 50m / 145-148 / 1 / BB
47 / Reliability / 50m / 148-159 / 1 / BB
48 / Scaling / 50m / 159,229 / 1,2 / BB
49 / SPICE tutorial, Device models / 50m / 181-193 / 1 / BB
50 / DeviceCircuit characterization, Interconnect simulation / 50m / 193 -213 / 1 / BB
CATII / 75m / - / - / -

DOC/LP/01/28.02.02

/ LESSON PLAN / LP – EC2354
LP Rev. No: 02
Date: 24/12/12
Page 06 of 06

Sub Code & Name: EC2354 VLSI DESIGN

Branch : EC Semester: VI

Course Delivery Plan:

Week / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13
I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II
Unit / / / / / / -
Test / - / T1 / T2 / T3 / T4 / T5 / T6 / T7 / T8 / CAT I / T9 / T10 / CAT II

Note: T1, …., T10: Weekly Test; CAT: Continuous Assessment Test

TEXT BOOKS:

  1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005
  2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCES:

  1. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003
  2. Wayne Wolf, Modern VLSI design, Pearson Education, 2003
  3. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997
  4. J.Bhasker: Verilog HDL primer, BS publication,2001
  5. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003
  6. Samir palnitkar, Verilog HDL , Pearson Education,second edition

Prepared by / Approved by

Signature

Name / Mr.M.Athappan / Ms.R.Kousalya / Dr.S.Ganesh Vaidyanathan
Designation / Assistant Professor / HoD - EC
Date / 24.12.2012 / 24.12.2012