Seminar Report 03Ovonic Unified Memory

Seminar Report ’03Ovonic Unified Memory

INTRODUCTION

We are now living in a world driven by various electronic equipments. Semiconductors form the fundamental building blocks of the modern electronic world providing the brains and the memory of products all around us from washing machines to super computers. Semi conductors consist of array of transistors with each transistor being a simple switch between electrical 0 and 1. Now often bundled together in there 10’s of millions they form highly complex, intelligent, reliable semiconductor chips, which are small and cheap enough for proliferation into products all around us.

Identification of new materials has been, and still is, the primary means in the development of next generation semiconductors. For the past 30 years, relentless scaling of CMOS IC technology to smaller dimensions has enabled the continual introduction of complex microelectronics system functions. However, this trend is not likely to continue indefinitely beyond the semiconductor technology roadmap. As silicon technology approaches its material limit, and as we reach the end of the roadmap, an understanding of emerging research devices will be of foremost importance in the identification of new materials to address the corresponding technological requirements.

If scaling is to continue to and below the 65nm node, alternatives to CMOS designs will be needed to provide a path to device scaling beyond the end of the roadmap. However, these emerging research technologies will be faced with an uphill technology challenge. For digital applications, these challenges include exponentially increasing the leakage current (gate, channel, and source/drain junctions), short channel effects, etc. while for analogue or RF applications, among the challenges are sustained linearity, low noise figure, power added efficiency and transistor matching. One of the fundamental approaches to manage this challenge is using new materials to build the next generation transistors.

PRESENT MEMORY TECHNOLOGY SCENARIO

As stated, revising the memory technology fields ruled by silicon technology is of great importance. Digital Memory is and has been a close comrade of each and every technical advancement in Information Technology. The current memory technologies have a lot of limitations. DRAM is volatile and difficult to integrate. RAM is high cost and volatile. Flash has slower writes and lesser number of write/erase cycles compared to others. These memory technologies when needed to expand will allow expansion only two-dimensional space. Hence area required will be increased. They will not allow stacking of one memory chip over the other. Also the storage capacities are not enough to fulfill the exponentially increasing need. Hence industry is searching for “Holy Grail” future memory technologies that are efficient to provide a good solution. Next generation memories are trying tradeoffs between size and cost. These make them good possibilities for development.

EMERGING MEMORY TECHNOLOGIES

Many new memory technologies were introduced when it is understood that semiconductor memory technology has to be replaced, or updated by its successor since scaling with semiconductor memory reached its material limit. These memory technologies are referred as ‘Next Generation Memories”. Next Generation Memories satisfy all of the good attributes of memory. The most important one among them is their ability to support expansion in three-dimensional spaces. Intel, the biggest maker of computer processors, is also the largest maker of flash-memory chips is trying to combine the processing features and space requirements feature and several next generation memories are being studied in this perspective. They include MRAM, FeRAM, Polymer Memory Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them will become the mainstream.

FUNDAMENTAL IDEAS OF EMERGING MEMORIES

The fundamental idea of all these technologies is the bistable nature possible for of the selected material. FeRAM works on the basis of the bistable nature of the centre atom of selected crystalline material. A voltage is applied upon the crystal, which in turn polarizes the internal dipoles up or down. I.e. actually the difference between these states is the difference in conductivity. Non –Linear FeRAM read capacitor, i.e., the crystal unit placed in between two electrodes will remain in the direction polarized (state) by the applied electric field until another field capable of polarizing the crystal’s central atom to another state is applied.

In the case of Polymer memory data stored by changing the polarization of the polymer between metal lines (electrodes). To activate this cell structure, a voltage is applied between the top and bottom electrodes, modifying the organic material. Different voltage polarities are used to write and read the cells. Application of an electric field to a cell lowers the polymer’s resistance, thus increasing its ability to conduct current; the polymer maintains its state until a field of opposite polarity is applied to raise its resistance back to its original level. The different conductivity States represent bits of information.

In the case of NROM memory ONO stacks are used to store charges at specific locations. This requires a charge pump for producing the charges required for writing into the memory cell. Here charge is stored at the ON junctions.

Phase change memory also called Ovonic unified memory (OUM), is based on rapid reversible phase change effect in materials under the influence of electric current pulses. The OUM uses the reversible structural phase-change in thin-film material (e.g., chalcogenides) as the data storage mechanism. The small volume of active media acts as a programmable resistor between a high and low resistance with > 40X dynamic range. Ones and zeros are represented by crystalline versus amorphous phase states of active material. Phase states are programmed by the application of a current pulse through a

MOSFET, which drives the memory cell into a high or low resistance state, depending on current magnitude. Measuring resistance changes in the cell performs the function of reading data. OUM cells can be programmed to intermediate resistance values; e.g., for multistate data storage.

MRAMs are based on the magnetoresistive effects in magnetic materials and structures that exhibit a resistance change when an external magnetic field is applied. In the MRAM, data are stored by applying magnetic fields that cause magnetic materials to be magnetized into one of two possible magnetic states. Measuring resistance changes in the cell compared to a reference performs reading data. Passing currents nearby or through the magnetic structure creates the magnetic fields applied to each cell.

OVONIC UNIFIED MEMORY

Among the above-mentioned non-volatile Memories, Ovonic Unified Memory is the most promising one. “Ovonic Unified Memory” is the registered name for the non-volatile memory based on the material called chalcogenide.

The term “chalcogen” refers to the Group VI elements of the periodic table. “Chalcogenide” refers to alloys containing at least one of these elements such as the alloy of germanium, antimony, and tellurium discussed here. Energy Conversion Devices, Inc. has used this particular alloy to develop a phase-change memory technology used in commercially available rewriteable CD and DVD disks. This phase change technology uses a thermally activated, rapid, reversible change in the structure of the alloy to store data. Since the binary information is represented by two different phases of the material it is inherently non-volatile, requiring no energy to keep the material in either of its two stable structural states.

The two structural states of the chalcogenide alloy, as shown in Figure 1, are an amorphous state and a polycrystalline state. Relative to the amorphous state, the polycrystalline state shows a dramatic increase in free electron density, similar to a metal. This difference in free electron density gives rise to a difference in reflectivity and resistivity. In the case of the re-writeable CD and DVD disk technology, a laser is used to heat the material to change states. Directing a low-power laser at the material and detecting the difference in reflectivity between the two phases read the state of the memory.

FIGURE 1

Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is working with several commercial partners to develop a solid-state nonvolatile memory technology using the chalcogenide phase change material. To implement a memory the device is incorporated as a two terminal resistor element with standard CMOS processing. Resistive heating is used to change the phase of the chalcogenide material. Depending upon the temperature profile applied, the material is either melted by taking it above the melting temperature (Tm) to form the amorphous state, or crystallized by holding it at a lower temperature (Tx) for a slightly longer period of time, as shown in Figure 2. The time needed to program either state is = 400ns. Multiple resistance states between these two extremes have been demonstrated, enabling multi-bit storage per memory cell. However, current development activities are focused on single-bit applications. Once programmed, the memory state of the cell is determined by reading its resistance.

FIGURE 2

Since the data in a chalcogenide memory element is stored as a structural phase rather than an electrical charge or state, it is expected to be impervious to ionizing radiation effects. This inherent radiation tolerance of the chalcogenide material and demonstrated write speeds more than 1000 times faster than commercially available nonvolatile memories make it attractive for space based applications. A radiation hardened semiconductor technology incorporating chalcogenide based memory elements will address both critical and enabling space system needs, including standalone memory modules and embedded cores for microprocessors and ASICs. Previously, BAE SYSTEMS and Ovonyx have reported on the results of discrete memory elements fabricated in BAE SYSTEMS’ Manassas, Virginia facility. These devices were manufactured using standard semiconductor process equipment to sputter and etch the chalcogenide material. While built in the same line used to fabricate radiation-hardened CMOS products, these memory elements were not yet integrated with transistors. They were discrete two-terminal programmable resistors, requiring approximately 0.6 mA to set the device into a low resistance state, and 1.3 mA to reset it to the high resistance state. One billion (1E9) write cycles between these two states were demonstrated. Reading the state of the device is non-destructive and has no impact on device wear out (unlimited read cycles).

OUM ATTRIBUTES

• Non volatile in nature
• High density ensures large storage of data within a small area
• Non destructive read:-ensures that the data is not corrupted during a read cycle.
• Uses very low voltage and power from a single source.
• Write/erase cycles of 10e12 are demonstrated
• Poly crystalline
• This technology offers the potential of easy addition of non volatile memory to a standard CMOS process.
• This is a highly scalable memory
• Low cost implementation is expected.

OUM ARCHITECTURE

A memory cell consists of a top electrode, a layer of the chalcogenide, and a resistive heating element. The base of the heater is connected to a diode. As with MRAM, reading the micrometer-sized cell is done by measuring its resistance. But unlike MRAM the resistance change is very large-more than a factor of 100. Thermal insulators are also attached to the memory structure in order to avoid data lose due to destruction of material at high temperatures.

To write data into the cell, the chalcogenide is heated past its melting point and then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just below its melting point and held there for approximately 50ns, giving the atoms time to position themselves in their crystal locations.

INTEGRATION WITH CMOS

Under contract to the Space Vehicles Directorate of the Air Force Research Laboratory (AFRL), BAE SYSTEMS and Ovonyx began the current program in August of 2001 to integrate the chalcogenide-based memory element into a radiation-hardened CMOS process. The initial goal of this effort was to develop the processes necessary to connect the memory element to CMOS transistors and metal wiring, without degrading the operation of either the memory elements or the transistors. It also was desired to maximize the potential memory density of the technology by placing the memory element directly above the transistors and below the first level of metal as shown in a simplified diagram in Figure 3.

FIGURE 3

To accomplish this process integration task, it was necessary to design a test chip with appropriate structures. This vehicle was called the Access Device Test Chip (ADTC) since each memory cell requires an access device (transistor) in addition to the chalcogenide memory element. Such a memory cell, comprised of one access transistor and one chalcogenide resistor, is herein referred to as a 1T1R cell. The ADTC included 272 macros, each with 2 columns of 10 probe pads. Of these, 163 macros were borrowed from existing BAE SYSTEMS’ test structures and used to verify normal transistor operation. There were 109 new macros designed to address the memory element features. These included sheet resistance and contact resistance measurement structures, discrete memory elements of various sizes and configurations, and two 16-bit 1T1R memory arrays.

Short loop (partial flow) experiments were processed using subsets of the full ADTC mask set. These experiments were used to optimize the process steps used to connect the bottom electrode of the memory element to underlying tungsten studs and to connect an additional tungsten stud level between Metal 1 and the top electrode of the memory element. A full flow experiment was then processed to demonstrate integrated transistors and memory elements.

FIGURE 4

Figure 4 shows the I-V characteristic for a 1T1R memory cell successfully fabricated using the ADTC vehicle. The voltage is applied to one of the two terminals of the chalcogenide resistor, and the access transistor (biased on) is between the other resistor terminal and ground. The high resistance amorphous material shows very little current below a threshold voltage (VT) of 1.2V. In this same region the low resistance polycrystalline material shows a significantly higher current. The state of the memory cell is read using the difference in I-V characteristics below VT. Above VT, both materials display identical I-V characteristics, with a dynamic resistance (RDYNAMIC) of ˜1k. In itself, this transition to a low resistance electrical state does not change the structural phase of the material. However, it does allow for heating of the material to program it to the low resistance state (1) or the high resistance state (0). Extrapolation of the portion of the I-V curve that is above VT to the X-axis yields a point referred to as a holding voltage (VH). The applied voltage must be reduced below VH to exit the programming mode.

FIGURE 5

Figure 5 shows the operation of a 1T1R memory, again with the access transistor biased on. The plotted resistance values were measured below VT, while the current used to program these resistances were measured above VT. Similar to the previously demonstrated stand-alone memory elements, these devices require approximately 0.6 mA to set to the low resistance state (RSET) and 1.2 mA to reset to the high resistance state (RRESET). The circuit was verified to be electrically open with the access transistor biased off.

FIGURE 6

Figure 6 shows the total dose (X-ray) response of N-channel transistors processed through the chalcogenide memory flow. The small threshold voltage shift is typical of BAE SYSTEMS’ standard radiation-hardened transistor processing. All other measured parameters (drive current, threshold voltage, electrical channel length, contact resistance, etc.) were also typical of product manufactured without the memory element.

CIRCUIT DEMONSTRATION

In order to test the behavior of chalcogenide cells as circuit elements, the Chalcogenide Technology Characterization Vehicle (CTCV) was developed. The CTCV contains a variety of memory arrays with different architecture, circuit, and layout variations. Key goals in the design of the CTCV were: 1) to make the read and write circuits robust with respect to potential variations in cell electrical characteristics; 2) to test the effect of the memory cell layout on performance; and 3) to maximize the amount of useful data obtained that could later be used for product design.The CTCV was sub-divided into four chiplets, each containing variations of 1T1R cell memory arrays and various standalone sub circuits. Standalone copies of the array sub circuits were included in each chiplet for process monitoring and read/write current experiments.

FIGURE 7

A diagram of one of the chiplets is shown in Figure 7. The arrays all contain 64k 1T1R cells, arranged as 256 rows by 256 columns. This is large enough to make meaningful analyses of parasitic capacitance effects, while still permitting four variations of the array to be placed on each chiplet. The primary differences between arrays consist of the type of sense amp (single-ended or differential) and variations in the location and number of contacts in the memory cell.

The data in the single-ended arrays is formatted as 4096 16-bit words (64k bits), and in the differential arrays as 4096 8-bit words (32k bits). The 256 columns are divided into 16 groups of 16. One sense amplifier services each group, and the 16 columns in each group are selected one at a time based on the four most significant address bits. In simulations, stray capacitance was predicted to cause excessive read settling time when more than 16 columns were connected to a sense amp. Each column has its own write current river, which also performs the column select function for write operations.