Schematic Simulation of a 4-To-1MUX Circuit

Experiment Week 9

Schematic simulation of a 4-to-1MUX circuit

A Report Presented to

Dr. Asim Al-Khalili

In Partial Fulfillment

of the Requirements

ofCOEN 451

Mathieu BouchardID: 9682775

Concordia University

Monday November 12th, 2012

Table of contents

Table of Figures

Objectives

Theory

Procedure

Results

Discussion

Conclusion

Table of Figures

Figure 1. 4-to-1 MUX With "Signal Boost" Feedback

Figure 2. 4-to-1 MUX Schematic

Figure 3. 4-to-1 MUX With "Signal Boost" Feedback Transient Response

Figure 4. 4-to-1 MUX Without "Signal Boost" Feedback Transient Response

Figure 5. 4-to-1 MUX With PMOS Width Increased to 8Wmin

Objectives

Study the pass gate effect on the transmission of signals

Study the effect of a “signal boost” feedback using an inverter and a PMOS transistor

Theory

This experiment studies the effect of the transistors used in the circuit presented in Figure 1. It represents a 4-to-1 multiplexer (MUX) with inputs A, B, C & D and control signals S0 & S1. The output is F and the point before the inversion i.e. before the feedback is identified by X.

Figure 1. 4-to-1 MUX With "Signal Boost" Feedback

The functionality of a multiplexer can be summarized briefly as follows. Depending on the value of the control signals S0 and S1, the nMOS transistor will turn on, allowing only one of the inputs to flow to the output. In this scenario, the inverter and the pMOS will boost the value of A in the case where it is one. This behavior will be studied in the following sections.

Procedure

A)Simulate the above circuit using SPICE. Use L = Lmin, Wn= 4Wmin and Wp= 2Wmin. Obtain F with A = S1 = S0 = 1.

B)Simulate the circuit and obtain F using the following input A = 0, S1 = S2 = 1.

C)Remove the pMOS and simulate with input A = 0, S1 = S2 = 1. Comment on the result.

D)Remove pMOS and inverter, obtain Output for A = S0 = S1 = 1. Comment on the results.

E)Now simulate the above circuit, using Wp= 8Wmin with input A = 0, S0 = S1 = 1. Comment on the result.

F)Optimize transistor sizes for the above 4-to-1 MUX.

Results

The circuit discussed in Figure 1 is simulated using the CMOSIS5 schematic simulation tools. Figure 2 represents the studied circuit.

Figure 2. 4-to-1 MUX Schematic

Using L = Lmin= 600nm, Wn=4Wmin = 9.6μm and Wp= 2Wmin = 4.8μm, Figure 3 shows the input, X and outputs signals of the MUX with conditions presented in steps A and B of the procedure.

Figure 3. 4-to-1 MUX With "Signal Boost" Feedback Transient Response

Similarly, Figure 4 demonstrates the behavior of the same 4-to-1 MUX, excepting the PMOS which is removed.

Figure 4. 4-to-1 MUX Without "Signal Boost" Feedback Transient Response

In order to further study the effect of the pMOS transistor parameters on the behaviour of the circuit, its width was increased to 8Wmin. The following figure presents the result obtained.

Figure 5. 4-to-1 MUX With PMOS Width Increased to 8Wmin

Discussion

The behaviour of the circuit studied in this experiment can be acknowledged when comparing Figure 3 and Figure 4. It is obvious that the voltage drop from 3.3V to 2.363V is due to the pass through the two nMOS along the path. The difference, ≈ 1V, is about 2Vtn. Thus, the feedback composed of the inverter and the pMOS recharges the weak ‘1’ produced into a strong ‘1’.

Furthermore, the modification of the width of the pMOS creates an expected effect on the passed signal (X) and the output voltage. When its width is increased, the parasitic capacitances increase. Therefore, the charging time of the capacitances of the transistor causes an incomplete discharge before the next pulse comes in. Indeed, the output voltage then stays constantly low.

Finally, according to the lab instructor, the optimization of the circuit is when all transistors have minimum sizes. Therefore, no calculations are required for part F.

Conclusion

Following this experiment, the objectives aimed have been achieved. The pass gate effect on the transmission of signals was studied. The current situation was not affected drastically but the addition of one or a few more transistors would completely change the designed behaviour. Moreover, the problem could be attenuated by the addition of buffers, most likely an inverter, every few transistors to regenerate the signal. This conclusion comes from the study of the effect of a “signal boost” feedback using an inverter and a PMOS for 4-to-1 multiplexer presented.