Sample and Hold Circuit

Sample and Hold circuit

Sample and Hold circuit using OPAMP The Sample and Hold (S&H) circuit is used when it is necessary to hold the sampled value of input signal for specified period of time. Thus sample and hold operation include two different processes: sampling the input signal and holding the latest sample value In this presentation we are going to discuss the basic sample and hold circuit first and then the sample and hold circuit using OPAMP. Basic sample and hold circuit The basic sample and hold circuit shown in fig has one input one output and an electronic switch which can be controlled by control signal. There are two possible mode of operation namely sampling mode and holding mode depending on the position of the switch. Sampling mode In this mode the switch is in the closed position and the capacitor charges to the instantaneous input voltage. This is sampling process. Hold mode In this mode this switch is in the “open” position .the capacitor is now disconnected from the input As there is no path for capacitor to discharge. It will hold the voltage which was present on it just before opening the switch. The capacitor will hold this voltage till the next sampling instant. Sample and Hold circuit using OPAMP The sample and hold circuit using OPAMP is shown in the fig and the relevant waveforms are shown in the fig The n channel MOSFET is driven by control voltage Vc act as a switch the control voltage Vc is applied to the gate of the MOSFET. Operation The circuit diagram of fig can be split into three stages: first stage is the voltage follower, second is the switch and capacitor and the third one is again the voltage follower. When Vc is high, the MOSFET turn on and act like a closed switch. This is sampling mode. The capacitor charges through the MOSFET to the instantaneous input voltage. As soon as Vc =0the MOSFET turns off and the capacitor is disconnected from OPAMP 1 output capacitor cannot discharge through amplifier A2 due to its high impedance Thus this the hold mode in which the capacitor hold mode on which the capacitor hold the latest sample value. Waveform for both these mode have been shown in fig Precaution The total period T=TH+TS as shown in fig where TH =holding time and TS=sampling time. The total period should be at least half of one cycle period of the input signal. In other words frequency of Vc should be at least twice the frequency of Vin. The capacitor C should be leak-proof. We can use the polystere or Teflon capacitors. Application of Sample and hold Circuit In the pulse modulation system. In the Analog and digital converter (ADC).

Simplified Sample and Hold Circuit

Analog Input sampled

Output from zero order hold.