Reference: STE10/100A Test Plan Revision 6

// 1 Aug 2008

// Reference: STE10/100A Test Plan Revision 6

// At-Spex LMO Test Systems

// Co-Authors: James Perry/ Danny ONeill

// Overview of Test:

// 1.Apply power to the DUT.

// 2. Reset DUT.

// 3.Read PCI Configuration Header via PCI port.

// 4.Configure DUT via PCI port.

// 4.Set up receive and transmit descriptors.

// 5.Enable PHY and wrap Ethernet transactions for 10 Mbps.

// 6.Go to 2 and repeat for 100 Mbps.

//------

//Register Initialization

//Operation Register Data Description

//------

//Read CR2 0x0200xxA1

//Read CR32 0x2774104A

//Write CR5 0x80000000 Set up MBA.

//Read CR5 0x80000000

//Write CR1 0x00000147 Turn on PERR#/SERR#.

//Read CR1 0x02800147

//Read CR15 0x00000100

//Write CSR0 0x0000C001 SW Reset.

//Read CSR5 xxxxxxxx x000000x xxxxxxxx xxxxxxxxb

//Read CSR0 0x0000C000 Need to write after reset.

//Write XR0 0x8000 Reset PHY.

//Write CSR25 0xBBAA0000

//Write CSR26 0xXXXXDDCC

//Write CSR3 0x88000000 Receive Descriptor Base Address

//Write CSR4 0x40000000 Transmit Descriptor Base Address

//------

//

//Wait 6 seconds for PHY reset to complete.

//

//------

//Write XR0 0x0100 Full Duplex.

//Read XR2 0x1C04 PHY ID

//Read XR3 0x0010 Model No.

//Read XR8 xxxxxx1x xxxxxxxxb

//Read XR0 0x3000 for 100 Mbps / 0x2000 for 10Mbps

//Read XR10

//Write CSR6 0x000820CA Turn on RX and TX/internal loopback

//------

//STE Reads TX DESCRIPTOR in 4 word burst

//STE Reads RX DESCRIPTOR in 4 word burst

//STE Reads TX BUFFER in 16 word burst

//------

//

//Read CSR5 0xFC365410 TX FIFO fill/RX wait for data/No Fatal bus error

//

//Wait 2000 cycles to give TX time to complete.

//

//Write CSR6 0x000000c8 Shut off RX/TX

//

//------

//STE Reads TX DESCRIPTOR in 4 word burst

//

//Withhold GNT from STE

//

//STE Writes RX BUFFER in 10-11 word burst

//

//Read XR10 xx00xx01 1x010100b

//

//------

//For XCVR loopback:

//STE Reads TX BUFFER

//STE Writes RXDESC0 0x0022AB26

//STE Writes TXDESC0 0x2A1B0000

//

//Read CSR5 0xFC71d550

//

//STE writes TXDESC0 0x1A170000

//------

//For MAC loopback:

//STE Writes RX BUFFER FCS in 2 word burst

// 0xA3396430

// 0x00441008

//STE Reads TX BUFFER

//STE Writes RXDESC0 0x00441300

//STE Writes TXDESC0 0x2A190000

//

//Read CSR5 0xFC71d550

//

//STE writes TXDESC0 0x1A170000

//------

//Descriptor Initialization

//Contents Description

//------

//0x80000000 TXDES0

//0x62000040 TXDES1 64byte message buffer

//0xA0000000 TXDES2

//0x00000000 TXDES3

//------

//0x80000000 RXDES0

//0x02000080 RXDES1

//0xC0000000 RXDES2

//0xD0000000 RXDES3

//------

#include "ste10.def"

vFormat

PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;

// D LLLVV

//P F CCCCE EEECA

//C R I////T IVS PS I B BB B BBBDDDCU

//I R A R G AA A A BBBBR DS R T EEN P R RR R RRRMMMDX E

//C S M D N D D D D EEEED SE EO RR PT M A AA D COW111ED BBE

//L T E Y T 3 2 1 0 nnnnY EL QP RR AA E 1 00 0 SEELFSTE DDC

//K n n n n 1 3 5 7 3210n Ln nn nn Rn n 6 87 4 nnnKDPET 67S

//------

Start:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.1000

Reset_uut:

K 0 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.101000

K 0 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Originally waited 34 seconds worst case PCI spec

//;ldlc.340

Reset_deassert:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.100000

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//;Loop.Reset_deassert

// Minimum 5 clocks after Reset# deasserted before Frame# asserted PCI Spec Rev 2.2 Section 4.3.2 Reset

// Maximum 2**25 clocks after Reset# deasserted before first access

//------

Read_Config_Hdr:

//Read CR2 Should be: 0200XXA1h

K 1 0 1 1 0000000000000000 00000000 00001000 1010X 1X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CR2:

K 1 1 0 1 LLLLLLHLLLLLLLLL XXXXXXXX HLHLLLLH 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CR2

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CR2

//Read_CR32

//Should be: 2774104Ah

K 1 1 1 1 0000000000000000 00000000 10000000 0000H 0H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 1010H 1H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CR32:

K 1 1 0 1 LLHLLHHHLHHHLHLL LLLHLLLL LHLLHLHL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CR32

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CR32

Write_CR5:

//Set MBA Register

K 1 1 1 1 0000000000000000 00000000 00010100 0000X 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 1011H 1H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_1:

K 1 1 0 1 1000000000000000 00000000 00000000 0000L 0L XX HX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_1

K 1 1 0 1 1000000000000000 00000000 00000000 0000X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CR5

//Read_CR5

//Should be: 0x80000000

K 1 1 1 1 0000000000000000 00000000 00010100 0000H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 1010H 1H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CR5:

K 1 1 0 1 HLLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CR5

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CR5

Write_CR1:

//Set Memory Space Access

K 1 1 1 1 0000000000000000 00000000 00000100 0000X 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 1011H 1H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_2:

K 1 1 0 1 0000000000000000 00000001 01000111 0000L 0L XX HX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_2

K 1 1 0 1 0000000000000000 00000001 01000111 0000X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CR1

//Read_CR1

//Should be: Read-only Bits 25 and 23 should be H, bits 2,1,0 should be H

// K 1 1 1 1 0000000000000000 00000000 00000100 0000H 0H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//K 1 0 1 1 ################ ######## ######## 1010H 1H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;ldlc.15

//Read_CR1:

//K 1 1 0 1 XXXXXXHX HXXXXXXX XXXXXXXH XHXXXHHH 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;Match.Read_CR1

//K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;JmpFail.No_Read_CR1

//Read_CR15

K 1 1 1 1 0000000000000000 00000000 00111100 0000H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 1010H 1H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CR15:

K 1 1 0 1 LLLLLLLL LLLLLLLL LLLLLLLH LLLLLLLL 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CR15

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CR15

//------

Write_CSR0:

//Reset MAC; MBA offset = 0

K 1 1 1 1 1000000000000000 00000000 00000000 0000X 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_3:

K 1 1 0 1 0000000000000000 11000000 00000001 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_3

K 1 1 0 1 0000000000000000 11000000 00000001 0000X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR0

//Read_CSR5--NOTE: Don't read until after sw reset to avoid erroneous error messages

//Check PHY stopped; MBA offset = 28h

K 1 0 1 1 1000000000000000 00000000 00101000 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CSR5:

K 1 1 0 1 XXXXXXXXXLLLLLLX XXLXXXXX XXXXXXXX 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CSR5

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CSR5

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

Wait_Control_reset_done:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.10

//------

Write_CSR0_1:

//MBA offset = 0

K 1 1 1 1 1000000000000000 00000000 00000000 0000X 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_3a:

K 1 1 0 1 0000000000000000 11000000 00000000 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_3a

K 1 1 0 1 0000000000000000 11000000 00000000 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR0

//Read_CSR0

//Check PHY stopped; MBA offset = 00h

K 1 0 1 1 1000000000000000 00000000 00000000 0110X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CSR0:

K 1 1 0 1 XXXXXXXL LXLXXLLX HHLLLLLL LLLLLLLL 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CSR0

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CSR0

Write_XR0:

//Reset PHY; MBA offset = b4h

K 1 1 1 1 1000000000000000 00000000 10110100 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_4:

K 1 1 0 1 0000000000000000 10000000 00000000 1100L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_4

K 1 1 0 1 0000000000000000 10000000 00000000 1100X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_XR0

//Write to CSR25 (PAR0)= BB, AA, 00, 00 and CSR26 (PAR1) = XX, XX, DD, CC

Write_MAC_Addr:

K 1 1 1 1 1000000000000000 00000000 10100100 0000X 0H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_5:

K 1 1 0 1 1011101110101010 00000000 00000000 0000L 0L XX HX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_5

K 1 1 1 1 1011101110101010 00000000 00000000 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;JmpFail.No_Write_CSR25

@@ . . u u ...... u . u u u u u . u u ......

K 1 1 1 1 1000000000000000 00000000 10101000 0000X 0H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_6:

K 1 1 0 1 0000000000000000 11011101 11001100 0000L 0L XX HX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_6

K 1 1 1 1 0000000000000000 11011101 11001100 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR26

//Write to CSR3; MBA offset = 18h

//RX_Ptr = 88000000h

Write_RX_Ptr:

K 1 1 1 1 1000000000000000 00000000 00011000 0000X 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_7:

K 1 1 0 1 1000100000000000 00000000 00000000 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_7

K 1 1 1 1 1000100000000000 00000000 00000000 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR3

//Write to CSR4; MBA offset = 20h

//TX_Ptr = 40000000h

Write_TX_Ptr:

K 1 1 1 1 1000000000000000 00000000 00100000 0000X 0H XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_8:

K 1 1 0 1 0100000000000000 00000000 00000000 0000L 0L XX HX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_8

K 1 1 1 1 0100000000000000 00000000 00000000 0000X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR4

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

// wait six seconds for PHY reset to complete.

;ldlc.60

Wait_PHY_reset_done:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.100000

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Loop.Wait_PHY_reset_done

//------

//Write_XR0:

//Loopback_Debug--turn-on internal loopback at XR0 [14] (XLBEN)

//vector 69:

K 1 1 1 1 1000000000000000 00000000 10110100 0000X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_8a:

//K 1 1 0 1 0000000000000000 00110010 00000000 1100L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 1 0 1 0000000000000000 01000001 00000000 1100L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_8a

//K 1 1 1 1 0000000000000000 00110010 00000000 1100X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 1 1 1 0000000000000000 01000001 00000000 1100X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_XR0

//------

//Read XCVR PHYID 1

//Read_XR2

K 1 0 1 1 1000000000000000 00000000 10111100 0110X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_XR2:

K 1 1 0 1 XXXXXXXXXXXXXXXX LLLHHHLL LLLLLHLL 1100L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_XR2

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_XR2

//Read XCVR PHY ID 2 and Model and Revision No.

//Read_XR3

K 1 0 1 1 1000000000000000 00000000 11000000 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_XR3:

K 1 1 0 1 XXXXXXXXXXXXXXXX LLLLLLLL LLLHLLLL 1100L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_XR3

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_XR3

//Test 10MBps

//Read XCVR Configuration and Interrupt Status XR8 [9:8] SPEED/DUPLEX bits to verify speed selection is correctly set to 0 for 10/ 1 for 100

//Read_XR8

K 1 0 1 1 1000000000000000 00000000 11010100 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_XR8:

K 1 1 0 1 XXXXXXXXXXXXXXXX XXXXXXLH XXXXXXXX 1100L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_XR8

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_XR8

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Read XCVR Control Register XR0 [15] XRST to verify PHY reset complete

//Read_XR0

K 1 0 1 1 1000000000000000 00000000 10110100 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_XR0:

K 1 1 0 1 XXXXXXXXXXXXXXXX LHLLLLLH LLLLLLLL 1100L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_XR0

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_XR0

//Read_XR10

//K 1 0 1 1 1000000000000000 00000000 11011100 0110X 0X XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;ldlc.15

//Read_XR10:

//K 1 1 0 1 XXXXXXXXXXXXXXXX XXLLXXLH HXLLLLLL 1100L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;Match.Read_XR10

//K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;JmpFail.No_Read_XR10

//Write Network Access Register

Write_CSR6:

K 1 1 1 1 1000000000000000 00000000 00110000 0000X 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_9:

//No internal loopback

K 1 1 0 1 0000000000001000 00100000 11001010 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Enable internal loopback

//K 1 1 0 1 0000000000001000 00100100 11001010 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_9

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR6

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// ;Rep.1000

//Read_XR10

//K 1 0 1 1 1000000000000000 00000000 11011100 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;ldlc.15

//Read_XR10:

//K 1 1 0 1 XXXXXXXXXXXXXXXX XXLLXXLH HXLLLLLL 1100L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;Match.Read_XR10

//1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//;JmpFail.No_Read_XR10

// K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//------

;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after TX turned on

Wait_TX_Desc_REQ:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_TX_Desc_REQ

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_REQ

//GNT# REQ#

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// ;ldlc.17

//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61

Wait_Memory_Access_1:

K 1 L H 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHL1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_Memory_Access_1

//Delays driving bus one clock--klunk vs. PCI timing

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_Access

//Read TXDES0--own bit set for STE10

K 1 L L 0 1000000000000000 00000000 00000000 XXXX0 00 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Read TXDES1, 2, 3

//was 32 byte size = 6 bytes x 2 addr + 2 bytes length + 18 data bytes; CSR18 default is 64bytes

K 1 L L 0 0110001000000000 00000000 01000000 LLLL0 00 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Buffer Address

K 1 L L 0 1010000000000000 00000000 00000000 LLLL0 00 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 0000000000000000 00000000 00000000 LLLL0 00 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Request PCI Access:

;ldlc.100

//Wait for UUT to access RX Descriptor Buffer Address

Wait_RX_Descriptor_REQ:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_RX_Descriptor_REQ

//GNT# REQ#

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_RX_Desc_REQ

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// ;ldlc.17

//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61

Wait_Memory_Access_2:

K 1 L X 0 HLLLHLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHL1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_Memory_Access_2

//Delays driving bus one clock--klunk vs. PCI timing

//Read RXDES0

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_RX_Desc_Access

K 1 L L 0 1000000000000000 00000000 00000000 XXXX0 00 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Read RXDES1, 2, 3

K 1 L L 0 0000001000000000 00000000 10000000 LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1100000000000000 00000000 00000000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 0000000000000000 00000000 00000000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Wait for UUT to access TX Descriptor Buffer Address

;ldlc.100

Wait_TX_Buffer_REQ:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_TX_Buffer_REQ

//GNT# REQ#

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Buffer_REQ

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

Wait_BufferMemory_Access_1:

K 1 L X 0 HLHLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_BufferMemory_Access

K 1 L L 0 1111111111111111 11111111 11111111 LLLL 0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1111111111111111 00000000 00000000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1011101110101010 11011101 11001100 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000000000101110 00000000 00000001 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000001000000011 00000100 00000101 LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000011000000111 00001000 00001001 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000101000001011 00001100 00001101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000111000001111 00010000 00010001 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1010101001010101 10101010 01010101 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1010010110100101 10100101 10100101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0101101001011010 01011010 01011010 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000000011111111 00000000 11111111 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1111111100001111 11110000 00000000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0101101011110000 00001111 10100101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0001001000110100 01010110 01111000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 1001101010111100 11011110 11110000 LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Read_CSR5

//Check PHY stopped; MBA offset = 28h

K 1 0 1 1 1000000000000000 00000000 00101000 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CSR5_status_3:

K 1 1 0 1 HHHHHHLLLLHHLHHL LHLHLHLL LLLHLLLL 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CSR5_status_3

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CSR5

//------

//Wait longer for message to complete transmission

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.2000

//------

//Write Network Access Register

Write_CSR6_2:

K 1 1 1 1 1000000000000000 00000000 00110000 0000X 0H XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 0 1 1 ################ ######## ######## 0111H 0H XX XX #X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

target_ready_9a:

//No internal loopback

K 1 1 0 1 0000000000000000 00000000 11001000 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Enable internal loopback

//K 1 1 0 1 0000000000000000 00000100 11001000 0000L 0L XX HX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

;Match.target_ready_9a

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Write_CSR6

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Wait 100 clocks for a PCI REQ# from UUT after TX turned on

;ldlc.100

Wait_Memory_Access_3:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_Memory_Access_3

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_REQ

//GNT# REQ#

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

Memory_Access_3:

//vector 140:

K 1 L H 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHL1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Reread TXDES0--own bit set for STE10

K 1 L L 0 1000000000000000 00000000 00000000 XXXX0 00 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Reread TXDES1, 2, 3

//CSR18 default is 64bytes

K 1 L L 0 0110001000000000 00000000 01000000 LLLL0 00 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Buffer Address

K 1 L L 0 1010000000000000 00000000 00000000 LLLL0 00 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 0000000000000000 00000000 00000000 LLLL0 00 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Withhold grant from UUT:

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Rep.10000

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Wait for UUT to write RX Buffer:

;ldlc.1000

Wait_Write_RX_Buffer_REQ:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_Write_RX_Buffer_REQ

//GNT# REQ#

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_RX_Buffer_REQ

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

RX_Buffer_Access:

K 1 L X 0 HHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 HHHHHHHHHHHHHHHH LLLLLLLL LLLLLLLL LLLL 0 0 0 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 LLHLHHLHLLHLHLHL HHLHLHLH LLHLHLHL LLLL 0 0 0 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// should be 0xBBAADDC

// K 1 L L 0 HLHHHLHHHLHLHLHL HHLHHHLH HHLLHHLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 HHLHLLHLHLHLHHLH LLHLHHLH LLHLHHLH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 X X 0 LLLLLLLLLLHLHHHL LLLLLLLL LLLLLLLH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 X X 0 HLLLLLLLLHLHLLHL HHLHLLHL HHLHLLHL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 X X 0 LLLLLLHLLLLLLLHH LLLLLHLL LLLLLHLH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 X X 0 HHHHHHHHHHHHHHHH HLLLLLLL LHHHHHHH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 X X 0 LLLLLHHLLLLLLHHH LLLLHLLL LLLLHLLH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 X X 0 LLHLHHLHLLLLLLLL LHHHHLLL LLLLLHHH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LLLLHLHLLLLLHLHH LLLLHHLL LLLLHHLH LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 HHLLLLHHHHLHLLHL HLLLLHHH HHHHHLLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LLLLHHHLLLLLHHHH LLLHLLLL LLLHLLLH LLLL0 00 LX XX LX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 HLLLLHHHHHHHLHHL HHHLLHLH HHLHLHLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 HLHLHLHLLHLHLHLH HLHLHLHL LHLHLHLH LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 LLHLLLHLLLHHLLHL HLHLLLLH HLLHLLLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 HLHLLHLHHLHLLHLH HLHLLHLH HLHLLHLH LLLL0 00 LX XX LX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 L L 0 LLHLLLHLLLHHLLHL LHLHHLLL LHHLHHLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LHLHHLHLLHLHHLHL LHLHHLHL LHLHHLHL LLLL0 00 LX XX LX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 H L 0 LLLLLLLLLLHLLLHL HLHLHLLL LLHLHHHL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LLLLLLLLHHHHHHHH LLLLLLLL HHHHHHHH XXXX0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

// K 1 H L 0 LLLLLLLLLLHLLHHL HLHLHLLL LLHLHHHL XXXX0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 HHHHHHHHLLLLHHHH HHHHLLLL LLLLLLLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LHLHHLHLHHHHLLLL LLLLHHHH HLHLLHLH LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 LLLHLLHLLLHHLHLL LHLHLHHL LHHHHLLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 L L 0 HLLHHLHLHLHHHHLL HHLHHHHL HHHHLLLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 H L 0 LLLHLLHLLLHHLHLL LHLHLHHL LHHHHLLL LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 H L 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after RX data received

Wait_TX_BUF_REQ_2:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_TX_BUF_REQ_2

//GNT# REQ#

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_REQ

//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61

//Read TX Buffer Address = 0xA0000000

Wait_Memory_Access_4_2:

K 1 L H 0 HLHLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHL1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// ;JmpFail.No_BufferMemory_Access

K 1 L L 0 1111111111111111 11111111 11111111 LLLL0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1111111111111111 00000000 00000000 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1011101110101010 11011101 11001100 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000000000101110 00000000 00000001 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000001000000011 00000100 00000101 LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000011000000111 00001000 00001001 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000101000001011 00001100 00001101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000111000001111 00010000 00010001 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1010101001010101 10101010 01010101 LLLL 0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1010010110100101 10100101 10100101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0101101001011010 01011010 01011010 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0000000011111111 00000000 11111111 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 1111111100001111 11110000 00000000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0101101011110000 00001111 10100101 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 L L 0 0001001000110100 01010110 01111000 LLLL0 00 LX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 1001101010111100 11011110 11110000 LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Wait for UUT to write RX Descriptor with status:

;ldlc.1000

Wait_UUT:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_UUT

//GNT# REQ#

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_RX_Desc_REQ

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

Wait_Access:

K 1 L X 0 HLLLHLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 LLLLLLLLLLHLLLHL HLHLHLHH LLHLLHHL LLLL 0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

;ldlc.100

Wait_Memory_Access_6:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_Memory_Access_6

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_Access

//GNT# REQ#

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

Memory_Access_6:

K 1 L H 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 0 LLHLHLHLLLLHHLHH LLLLLLLL LLLLLLLL LLLL0 00 LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//Read_CSR5

K 1 0 1 1 1000000000000000 00000000 00101000 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CSR5_status_2:

K 1 1 0 1 HHHHHHLLLHHHLLLH HHLHLHLH LHLHLLLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CSR5_status_2

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CSR5

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//Read_XR10

K 1 0 1 1 1000000000000000 00000000 11011100 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_XR10:

K 1 1 0 1 XXXXXXXXXXXXXXXX XXLLXXLH HXLHLHLL 1100L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_XR10

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_XR10

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after RX data received

Wait_RX_FCS_WRITE_REQ:

K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Wait_RX_FCS_WRITE_REQ

//GNT# REQ#

K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_TX_Desc_REQ

//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61

//Write RX Buffer Location 16/17 (17th/18th writes) Address = 0xc0000040

Wait_Memory_Access_4:

K 1 L H 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

K 1 H L 1 LLLHHLHL LLLHLHHH LLLLLLLL LLLLLLLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

// K 1 H L 1 LLLLLLLL LHLLLHLL LLLHLLLL LLLLHLLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//------

//Read_CSR5

K 1 0 1 1 1000000000000000 00000000 00101000 0110X 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;ldlc.15

Read_CSR5_status:

K 1 1 0 1 HHHHHHLLLHHHLLLH HHLHLHLH LHLHLLLL 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;Match.Read_CSR5_status

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;JmpFail.No_Read_CSR5

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

//------

//;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after TX turned on

//Wait_Memory_Access_5:

// K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// ;Match.Wait_Memory_Access_5

// K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// ;JmpFail.No_RX_Desc_REQ

//GNT# REQ#

//K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//Write to RX Desc0

//Memory_Access_5:

// K 1 L H 0 HLLLHLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// K 1 H L 0 LLLLLLLLLHLLLHLL LLLHLLHH LLLLLLLL LLLL0 00 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//------

//------

//Wait for UUT to write TX Descriptor with status:

// ;ldlc.1000

//Wait_UUT:

// K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// ;Match.Wait_UUT

//GNT# REQ#

// K 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

// ;JmpFail.No_TX_Desc_REQ

//K 1 X X 0 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

//Wait_Access:

// K 1 L X 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

//@@ . . u u ...... u . u u u u u . u u ......

Finish:

// K 1 H L 0 LLLHHLHLLLLHLHHH LLLLLLLL LLLLLLLL LLLL 0 00 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

K 1 H H 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

@@ . . u u ...... u . u u u u u . u u ......

;halt

//------

//Add change to set to high speed on PHY and jump to waiting for descriptor access

//------

// ;jmp.Reset_uut //continuous loop

//------

//vector 207

//Error Detection:

No_Read_CR2:

1 1 1 0 1 LLLLLLHLLLLLLLLL XXXXXXXX HLHLLLLH 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_CR32:

1 1 1 0 1 LLHLLHHHLHHHLHLL LLLHLLLL LHLLHLHL 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CR5:

1 1 1 0 1 1000000000000000 00000000 00000000 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_CR5:

1 1 1 0 1 HLLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CR1:

1 1 1 0 1 0000000000000000 00000000 00000111 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

//No_Read_CR1:

// 1 1 1 0 1 XXXXXXHX HXXXXXXX XXXXXXXH XHXXXHHH 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

// ;halt

No_Read_CR15:

1 1 1 0 1 LLLLLLLL LLLLLLLL LLLLLLLH LLLLLLLL 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_CSR5:

1 1 1 0 1 HHHHHHHHHHHHHHHH HHHHHHHH HHHHHHHH 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_CSR0:

1 1 1 0 1 XXXXXXXX LXLXXLLX HHLLLLLL LLLLLLLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR0:

1 1 1 0 1 0000000000000000 00000000 00000001 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_XR0:

1 1 1 0 1 0000000000000000 10000000 00000000 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR25:

1 1 1 0 1 1011101110101010 00000000 00000000 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR26:

1 1 1 0 1 0000000000000000 11011101 11001100 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR3:

1 1 1 0 1 1000100000000000 00000000 00000000 0000L 0L XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR4:

1 1 1 0 1 0100000000000000 00000000 00000000 0000L 0L XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_XR2:

1 1 1 0 1 XXXXXXXXXXXXXXXX LLLHHHLL LLLLLHLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_XR3:

1 1 1 0 1 XXXXXXXXXXXXXXXX LLLLLLLL LLLHLLLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_XR8:

1 1 1 0 1 XXXXXXXXXXXXXXXX XXXXXXLX XXXXXXXX 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Read_XR0:

1 1 1 0 1 XXXXXXXXXXXXXXXX LLLLLLLL LLLLLLLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_Write_CSR6:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 XX XX 0X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

//vector 226:

No_Read_XR10:

1 1 1 0 1 XXXXXXXXXXXXXXXX XXLLXXLH HXLHLHLL 0000L 0L XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_TX_Desc_REQ:

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_TX_Desc_Access:

1 1 L H 0 LHLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL LHHH1 01 XX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_RX_Desc_REQ:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_RX_Desc_Access:

K 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X XX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_BufferMemory_Access:

1 1 1 1 1 LLLLLLLLLLLLLLLL LLLLLLLL LLLLLLLL XXXXX 0X LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_TX_Buffer_REQ:

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_TX_Buffer_REQ_2:

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_TX_Buffer_REQ_3:

1 1 1 1 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXXX 0X LX XX 1X X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

No_RX_Buffer_REQ:

1 1 X X 1 XXXXXXXXXXXXXXXX XXXXXXXX XXXXXXXX XXXX1 01 LX XX XX X XXXXXXXXXXXXXXXXX XXXXX XXXXXX10 XXX

;halt

//------

//Don't add below here!

//compiler likes line feeds after halt microinstruction