Table of Contents

Table of Contents...... 2

Table of Contents...... 2

1 Introduction...... 3

1.1 Vision3

1.2 Background...... 3

1.3 Objectives...... 3

1.4 Deliverables...... 3

1.5 Expected Project Benefits...... 3

1.6 Core Team Members...... 3

2 Strategy & Approach...... 4

2.1 Assumptions & Constraints...... 4

2.2 Issues & Risks...... 4

3 System Level Architecture...... 5

4 PWM Sine Wave Generator...... 6

1Introduction

1.1Vision

The mission of this project is to design, build and test a scalable prototype of a thermal heater controller for the Space Systems Division of ITT. The controller will be subsystem in future satellite-imaging systems.

1.2Background

The Satellite Thermal Heater Controller (STHC) is a single master multiple slave system that can be arrayed in a distributed fashion with centralized control. The system can be described as a group of distributed, autonomous thermal control units that share the same power input, which will also serve for communication. This controller may be used in satellite applications to control the temperature of critical optical subsystems.

1.3Objectives

  1. Demonstrate an enhancement to ITT's current distributed autonomous thermal controller.
  2. Create a more competitive thermal controller that is lightweight, scalable, modular, reliable, cost effective and power efficient.
  3. Demonstrate the ability to thermally control, stabilize and enable critical optical subsystems.
  4. Selecting components that will minimize power consumption, weight and cost, respectively.
  5. Achieve communications between the master and slaves through the DC power line.
  6. Program DSP for efficient communication between master and slaves.
  7. Connect DSP to heater controller to communicate between slaves and heater controllers.
  8. Design HHC enclosure to meet vibration, thermal conductivity, EMI, and venting specs.

1.4Deliverables

  1. Interface electronics to send information between the master and slave DSP board over heater power bus.
  2. PC interface that communicates with master over serial line.
  3. Programming of master to accept requests from the PC and pass them on to slave
  4. Programming of slave to control HHC and send status back to master.
  5. PC GUI to monitor and control the temperature and state of (2) heater controllers.

1.5Expected Project Benefits

  1. The STHC shall be used as a basis for future heater control systems launched and deployed in space by ITT to regulate the temperature of a variety of satellite payloads.
  2. The STHC might be used by other groups that are involved in satellite imaging applications.
  3. Reinforce the engineering programs at RIT.

1.6Core Team Members

  1. Anthony Berwin
  2. Scott Rioux
  3. Greg Pawlowski
  4. Sarmad Abedin
  5. John Scipione

2Strategy & Approach

2.1Assumptions & Constraints

  1. There is a time constraint of 22 weeks where the project must be completed.
  2. Lead times for parts components and materials. Incorporate lead times into scheduling.
  3. Lead time for printed circuit boards. Incorporate lead times into scheduling.
  4. Controller from the Texas Instruments (28x family).
  5. Access to the Hybrid Heater Controller (HHC) Specifications.

2.2Issues & Risks

Acquiring HHC / Need one for testing and demo
Programming Difficulty / Consultation with faculty and advisors, Jerome Barczykowski
Hardware Interface / Build and lead times, parts are common should not be a problem
Equipment Failure / Buy new stuff
Time constraints / Difficult programming, time to finish and build and test
Testing equipment / Replacing and using new equipment, understand specs
Code Composer Complications / Further Research and training
Analog to Digital Converter Programming Complications / Further Research and training

3System Level Architecture

Figure 3.1: System Level Architecture

4PWM Sine Wave Generator

The Texas Instruments TMS320F2808 DSP is used to communicate between the master and slave DSPs over the 22 AWG wire. Because only one communication wire is available FSK signal generation is necessary to communicate between the two DSPs. The transmitted FSK signal is generated using the pulse width modulator (PWM) of the TMS320F2808 of the EZDSP. The transmitted signal will pass through a passive low-pass filter to smooth the signal and generates a sine wave.

The PWM signal outputs on a TMS320F2808 device are variable duty cycle square waves with 3.3 volt amplitude. These signals can each be decomposed into a DC component plus a new square wave of identical duty-cycle but with a time-average amplitude zero.

The idea behind realizing digital-to-analog (DA) output from a PWM signal is to apply an analog low-pass filter the PWM output to remove most of the high frequency components leaving only the DC component. The bandwidth of the low-pass filter will essentially determine the bandwidth of the digital-to-analog converter.

Two main sources of error negatively affect the DA output. Firstly, the PWM duty cycle can only be specified with a finite resolution. The resolution is directly related to the PWM carrier frequency used. For example, suppose 100 kHz PWM is desired with the PWM module driven by a 100 MHz SYSCLKOUT. The time-base of the PWM will provide 1000 clock counts per cycle of PWM at which to specify the timer compare value. This directly affects the duty cycle. If the standard PWM is used, the resulting resolution is just less than 10-bits. The desired DC output is specified in steps of 3.3 mV (3.3V/1000). However, using the enhanced PWM module (ePWM) provides approximately 6 additional bits of resolution beyond the standard time-base resolution. This equates to just under 16 bits of resolution.

The second source of error is the peak-to-peak ripple produced by unfiltered harmonics. The two error sources sum together to yield the total uncertainty:

total uncertainty = harmonic ripple + duty cycle resolution

The duty cycle resolution can be improved by decreasing the carrier frequency of the PWM. Reducing the carrier frequency from 100 kHz to 50 kHz will cut the step size in half to 1.65 mV (~11 bits resolution for the standard resolution PWM or ~17 bits resolution for the high resolution PWM). The lower carrier frequency also decreases the base frequency of the unwanted harmonics. The first harmonic will now appear at 50 kHz rather than 100 kHz, and more of it will pass through the analog low-pass filter increasing the harmonic ripple.

For a given analog low-pass filter a trade-off exists between the harmonic ripple and PWM duty cycle resolution when selecting the PWM carrier frequency. The optimal carrier frequency is the one where the total uncertainty is smallest.

The performance of the filtered PWM as a digital-to-analog converter depends heavily on the choice of the analog low-pass filter chosen. Active filters (built using op-amps) are often used rather than passive filters (built solely using resistors, inductors, and capacitors). Although active filters avoid the impedance loading issues suffered by passive filters, passive filters can offer lower cost and reduce complexity. The gain bandwidth of the op-amps must be considered when using active filters. The gain bandwidth represents the upper frequency that the op-amp can effectively handle when used in a closed-loop circuit configuration with small signal input. However, passive filters do not suffer as much from a gain bandwidth problem, although they do have their own high-frequency design issues (especially in designs that utilize inductors).

The two most important filter properties when selecting a low-pass filter are the bandwidth and the stop-band roll off rate. The filter bandwidth is the frequency at which the filter's frequency response magnitude equals 0.707 (-3 dB). The filter bandwidth directly relates to the maximum signal frequency that the PWM/DAC will handle effectively and the stop-band roll-off rate is the slope of the frequency response magnitude at high frequency. Combined with the bandwidth, the roll-off rate determines the amount of harmonic ripple that will be seen in the output of the filter. In general, low-pass analog filters roll-off at a rate of -20 dB/decade per filter order (-20 dB/decade for a 1st order filter, -40 dB/decade for a 2nd order filter, etc.).

For this design, a 2nd-order low-pass passive filter was chosen. The 2nd-order low-pass filter offers 40 dB/decade of stop-band roll-off -- a two-fold improvement over the 1st order filter. For a second order system, the transfer function is given by:


where ωn is the undamped natural frequency in units of (rad/s)2, and ζ is the damping ratio. The step response of the filter is an important measure of performance for the practical situation of changing the DAC output from one voltage level to another. It is important to get as low a damping ratio as possible in order to have fast rise times. However, low damping ratios produce large step response overshoots and long settling times. The smallest damping ratio with no overshoot in the step response is ζ=1 (critically damped). It is also desirable to avoid having a resonant peak in the frequency response magnitude of the filter. The smallest damping ratio with no resonant peak is ζ=0.707 (-3dB). The choice of damping ratio will depend on the particular requirements of your system. A reasonable trade-off is often to choose the filter damping ratio between 0.707 and 1.0.

A passive 2nd order passive RC filter is constructed by cascading two 1st order RC filters in series like so:




The following component values were chosen:

R1 = R2 = 1k

C1 = C2 = 0.01uF

This resulted in a cutoff frequency of

ωn = 100kHz

and a dampening ratio of

ζ = 1.5

A cutoff frequency ~100kHz is desirable for this particular application as it will cutoff most of the higher harmonic frequencies . The frequencies desired for this design are between 50Khz and 100Khz.

Higher order filters offer progressively better stop-band roll-off rates, and hence remove more of the unwanted ripple. However, design complexities associated with thermal drift and component value variation increase with filter order. Cost and board space also increases. At some point an actual DAC chip becomes a better solution than emulating one with a PWM/DAC.

Using the above designed filter, the next step is to produce the desired PWM function from the DSP.

The PWM frequency is derived from SYSCLKOUT = 100 MHz. The eZdsp 2808 is clocked from a 20 MHz oscillator. The CPU clock is initialized with SysCtrlRegs.PLLCR = 10. So that the CPU clock is running at CLKIN= 100 MHz. This clock feeds other module as SYSCLKOUT.

In order to generate the desired frequencies the SYSCLKOUT is divided down to a more reasonable frequency used by the HRPWM. The SYSCLKOUT is divided by 400 to give a PWM clock of 250Khz. The PWM clock is then divided down a second time to yield the desired frequency for a binary 0 or 1. For example

250kHz/4.1667 = 60kHz which represents a binary 0.

250kHz/2.7778 = 90kHz which represents a binary 1.

This PWM clock is fed into a table of sine values to vary the duty cycle of the output of the PWM. After the PWM signal is fed through the DAC a sine wave of the appropriate frequency results. In this way the PWM/DAC produces the correct frequency for a 0 or a 1. A division factor of 1 can be used to produce no output since 250Khz is above the cutoff frequency and thus will be filtered out by the low pass filter.

References

Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x –

Spread-Frequency Shift Keying Power Line Modem Software Architecture –