Electrical and Computer Engineering
ECE-C302
I. FPGA embedded Block RAM
Problem Statement
Implement Random Access Memory as block RAM generated by Core Generator tool.
Objective
To study and implement embedded block RAM.
Deliverable
Demonstrate a working RAM with interfaces to the S3 board switches, button and LEDs.
Steps
1. Create new ISE project
2. Add new source asCore Generator type (as opposed to vhdl module or UCF) name it “ram4_16”.Core Generator window will start.
3. In Core Generator window, generate single-port 16X4 RAM, that is, 16 locations or depth = 16 (4-bit address) and 4-bit data or width = 4. Choose options when generating the block RAM according to the port declaration below. For instance, the design can benefit from registered output data and it does not require error flags (intended to be a simple example). After the core has been generated, under ipcore (Intellectual Property core) ram4_16 open HDL functional and HDL for Instantiation; ram4_16.vhd and ram4_16.vho.
ENTITY ram4_16 IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
dina: IN std_logic_VECTOR(3 downto 0);
douta: OUT std_logic_VECTOR(3 downto 0));
END ram4_16;
The vhdl file ram4_16.vhd is for simulation. (This lesson does not do simulation).Open ram4_16.vho and familiarize with the following templates (e.g., the ports; wea = write enable, adda = address, din = data in, dout = data out).
-- The following code must appear in the VHDL architecture header:
------Begin Cut here for COMPONENT Declaration ------COMP_TAG
component ram4_16
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
dina: IN std_logic_VECTOR(3 downto 0);
douta: OUT std_logic_VECTOR(3 downto 0));
end component;
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ram4_16
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- INST_TAG_END ------End INSTANTIATION Template ------
4. Create new source, an entity called “myram”. It will contain ram4_16 as a component. The code is shown below. In UCF; connect din (data in), wen (write enable), addra (address) to switches and, dout (data out to LEDs. Implement and test myram.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity myram is
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
dina: IN std_logic_VECTOR(3 downto 0);
douta: OUT std_logic_VECTOR(3 downto 0));
end myram;
architecture Behavioral of myram is
component ram4_16
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
dina: IN std_logic_VECTOR(3 downto 0);
douta: OUT std_logic_VECTOR(3 downto 0));
end component;
begin
u1 : ram4_16
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
end Behavioral;
II. FIFO (First-In First-Out) Queue
Problem Statement
Implement a FIFOgenerated by Core Generator.
Objective
To study and implement aFIFO.
Deliverable
Demonstrate a working FIFO with interfaces to the S3 board switches, button and LEDs.
Steps
1. Create new ISE project
2. Add new source from Core Generator called “my_fifo”
3. With Core Generator application generate a FIFO according to the following ports (choose depthequal to 5)
entity my_fifo
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(3 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(3 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end my_fifo;
Open my_fifo ipcore vhd and vho files and look through the codes. As in myram design, designer opens the instantiation file (dot vho), copies and pastes the component template in the design containingthe ipcoreas a component.
4. Add new source, entity called“fifo”(the code is shown below). In UCF connect din (data in), wr_en (write enable, rd_en (read enable), srst (synchronous reset) to switches; b1, b2 (single-step buttons); and dout (data out), full, empty (flags) to LEDs. Implement and test fifo. Note the latency (3 clock cycles or 3 single steps) before the empty flag goes low and the data appears at dout LEDs. Verify the FIFO functions.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo is
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(3 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
b1, b2: IN std_logic;
dout: OUT std_logic_VECTOR(3 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end fifo;
architecture Behavioral of fifo is
signal en: std_logic;
type state is (s0, s1, s2);
signal n_s: state;
-- copied from instantiation file
component my_fifo
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(3 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(3 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
begin
-- copied from instantiation file
U1 : my_fifo
port map (
clk => en,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty);
-- single step state machine
process(clk)
begin
if clk'event and clk='1' then
case n_s is
when s0 => en <= '0';
if b1 = '1' then n_s <= s1; end if;
when s1 => en <= '1';
n_s <= s2;
when s2 => en <= '0';
if b2 = '1' then n_s <= s0; end if;
end case;
end if;
end process;
end Behavioral;
III. A design with FIFO (First-In First-Out) Queue
Modify the fifo design in Section 2 to automatically reads the contents off the FIFO when the full flag goes high every second until the queue is empty. Test the correctness by doing 5 writes and observing the LEDs displaying different written data every second. An approach is to have a state machine controlling the FIFO reads when the full flag is high and displays the data, at a one-second interval until empty flag is high.