Project PlanRev. 0.1Page 1
Project Bluebird
University of Portland / School of EngineeringPhone 503 943 73145000 N. Willamette Blvd. Fax 503 943 7316
Portland, OR 97203-5798
Final Report
Project Kokanee: TTL 7400 Series Logic Tester using CMOS VLSI
Contributors:
John McGlone
Drew Willis
Paul Berardi
Advisors/Industry Representative:
Dr. Albright, Dr. Osterberg, Steve Kassel
Approvals
Name / Date / Name / DateDr. Albright / Dr. Lillevik
Insert checkmark (√) next to name when approved.
University of PortlandSchool of EngineeringContact: P Berardi
Final ReportRev. 1.0Page 1
Project Kokaneeup-cs-tr-04-06
Revision History
Rev. / Date / Author / Reason for Changes0.9 / 03/29/04 / Paul, Drew, John / Initial draft
1.0 / 04/22/04 / Paul, Drew, John / Final draft
University of PortlandSchool of EngineeringContact: P Berardi
Final ReportRev. 1.0Page 1
Project Kokaneeup-cs-tr-04-06
Acknowledgements
Team Kokanee would like to recognize the contributions of our advisors, Dr. Robert Albright and Dr. Peter Osterberg for their wisdom and foresight throughout the entire design, development, and release of Project Kokanee. We would also like to thank Mr. Steve Kassel for sacrificing his valuable time to teach us tangible, real-world problems, solutions and lessons throughout the project. Many thanks to John Felton for helping us manufacture the housing for our project. Finally, we would like to thank our friends and family for all their behind the scenes support and reassurance.
Table of Contents
Summary
Introduction
Background
Methodology
Problem / Solution
VLSI Design Process
PIC Architecture Design Process
Testing
Chip Testing
Device Validation
Documentation
Results
Technical
General Description
Hardware Architecture
VLSI Chip
PIC Microcontroller
User Interface Architecture
Device Under Test (DUT)
Power Supply
Software Architecture
Initialization
User Menu / Wait State
DUT Routine
Testing Routine
Hardware Design
VLSI Chip
Counters
Flip-Flop Array
I/O Pads
MUX
Reset
PIC Hardware Design
Software Design
Process
Assumptions
Risks
Schedule
Resources
Conclusions
University of PortlandSchool of EngineeringContact: P Berardi
Final ReportRev. 1.0Page 1
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List of Figures
Figure 1. High-Level System Block Diagram
Figure 2. PIC Program Architecture
Figure 3. B2Logic VLSI Chip Circuit Schematic
Figure 4. Decoding / Encoding Circuitry
Figure 5. Low –Level Encoding / Decoding Circuitry
Figure 6. VLSI I/O Pad to DUT Interface
Figure 7. 16-to-1 MUX Block Diagram
Figure 8. VLSI Reset Circuitry
Figure 9. Software Testing Flow Chart
University of PortlandSchool of EngineeringContact: P Berardi
Final ReportRev. 1.0Page 1
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List of Tables
Table 1: Risks
Table 2: Milestones
Table 3: Original Budget
Table 4: Final Materials Budget
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Final ReportRev. 1.0Page 1
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Chapter / Summary1
Project Kokanee is a transistor-transistor logic (TTL) 7400 series functional tester implemented with a custom designed CMOS VLSI chip from MOSIS and a PIC18F series microcontroller. University of Portland students and faculty will use this project to test TTL 7400 series logic chips in the engineering microprocessor laboratory. This Final Report document discusses the entire process involved in the design, implementation, and documentation of Project Kokanee. The Theory of Operations document provides an overall review of Project Kokanee while discussing the methods of how we designed and implemented the project, the results of the project and the conclusions we have made as a result of going through the entire process.
Chapter 4, Methodology, provides an explanation of the steps taken to design, fabricate, test and document the TTL 7400 Series Logic Tester using CMOS VLSI. The methods sections starts by discussing the basic problem we faced with the project and solutions needed to solve the problem. Next, the process of the design and fabrication of the VLSI chip is discusses as well as the macro model. Then the process for creating the PIC architecture is gone over step by step. After describing the design process, the testing of the device is overviewed. Chapter 4 concludes with descriptions of the documentation for each phase of the project.
Chapter 5, Results, contains the bulk of information in this document. The first section provides a complete technical description of the functionality of our device as well as the interface of each major component in the system. The second half of the Results describes the process required to complete the project. This includes the assumptions made at the beginning of the project and the risks associated with those assumptions. Next the schedule of tasks is reviewed and analyzed showing our progress and delays. Finally, the budget is addressed comparing the original budget to the final budget.
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Chapter / Introduction2
The purpose of this document is to present a clear detailed description of the design and implementation process of Project Kokanee. The document provides a detailed view of the project’s methodology with regard to design, fabrication, testing and documentation. Users of the 7400 series functional tester and those who wish to reproduce and improve on the design of the functionality of the tester will find this document valuable. Readers wanting to gain insight on an engineering design project and the entire process, which encapsulates that, will also find this document to be of value. This document will include methodology processes as well as in-depth descriptions of how the logic tester functions.
The background section provides motivation for the design and implementation of Project Kokanee. The methods section describes the documentation process throughout development as well as the design and fabrication steps leading up to the prototype release. The results section contains the bulk of information in the document. It is parsed into two sections. The first segment consists of a brief technical description of the project covering both hardware and software. The second segment describes the original project plan while comparing it to the actual execution and analyzes the outcome. Finally, the conclusion section recognizes the major accomplishments, setbacks, and lessons learned throughout Project Kokanee.
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Chapter / Background3
The functional tester has been an integral piece of equipment in laboratories and manufacturing facilities since the invention of the transistor. The functional tester is meant to be a quick means of checking a device to see if it is in proper working condition. Currently at the University of Portland engineering facilities there is no such functional tester available for student and faculty use.
In the case of the 7400 series functional tester, two major components are incorporated. The first is a digital CMOS VLSI logic chip. VLSI stands for Very Large Scale Integrated circuit. The chip is composed of several hundred transistors placed on a single integrated circuit. VLSI technology is used in almost all electronics from computer processors to embedded systems. The VLSI chip was fabricated by the MOSIS Educational Program, which is based out of the University of Southern California.
The second major component of the 7400 series functional tester is the programmable integrated circuit (PIC) microcontroller. The PIC microcontroller is a cheap, viable and customizable way to manage an embedded system. Like VLSI logic, microcontrollers are used in a diverse number of applications from cell phones to automobiles.
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Chapter / Methodology4
This chapter outlines the basic steps taken to initiate and execute Project Kokanee. The first step was to identify the problem that the project faces and the resulting solution that is created. After that initial stage, the design and implementation phases are addressed followed by descriptions of all the documentation that support the progression.
Problem / Solution
The initial problem that we faced was the unreliability of integrated circuits (ICs) in the University of Portland microprocessor lab. The solution that we devised was a device that can quickly and reliably verify the functionality of an IC.
After that initial step, we began designing the system and encountered several basic problems. How will the user interact with the system? How will system test the device under test (DUT)? A simple solution
to both of these problems is to use a PIC microcontroller to control user the interface devices (keypad, liquid crystal display (LCD) screen, and light emitting diodes (LEDs)) and to send and receive test vectors to the DUT. Once the PIC was set as a system controller we realized that there were not enough I/O ports to control all of the peripheral devices as well as have one-to-one pin connections with the DUT. The solution to this predicament was to design a VLSI chip to use the least amount of I/O ports from the PIC to control the inputs and outputs of the DUT.
VLSI Design Process
The design process of the VLSI chip started with an informal brainstorming of hand designs and drawn schematics. Next, the design was constructed and tested in the B2Logic simulator. After verifying that the design was correct, a .tpr file was created which would be used for chip fabrication. The .tpr file describes every part and connection of the circuit that is placed on the chip. The .tpr file was checked and rechecked before sending it off for fabrication of the VLSI chip at MOSIS.
While the VLSI chip was being fabricated we created a discrete macro model that models the functionality of the VLSI chip. Various TTL 7400 logic chips were accrued along with the basic breadboard and wire wrapping necessities. The macro model was built and used for testing with the rest of the system to ensure that the VLSI design was correct. The macro model also allows for a secure backup incase the VLSI chip could not be produced correctly or on time.
PIC Architecture Design Process
The PIC architecture was a step-by-step process that started with the basic initiation and setup of the system including initializing all the peripherals and interface with the VLSI. After that was accomplished, the testing routines were implemented for one chip. By dynamically allocating test vector variables and setups, the addition of chip types was simple. Adding chips included placing their test vectors into memory and adding the appropriate subroutines into code. When all chips testing routines were completed the finalized menu screens were finalized.
Testing
Chip Testing
To properly test a chip we exhaustively tested every Boolean input into each logic gate. Testing further addressed other possible failure scenarios, which included taking samples of each chip type and tying each pin of the DUT to high voltage, low voltage or open / disconnected. We also tested placing chips in to the zero insert force (ZIF) socket backwards and placing chips of a different type then selected into the ZIF socket. The 75 scenarios that we tested all provided expected results.
Device Validation
To validate that our device worked properly and met our original design requirements we went through the process of checking our functional specifications to see that what we had listed matched our end design. The results that we found were, that our device accurately tests the functionality of the selected IC, testing of an IC is conducted in a timely manner, that the user interface was simple and easy to use, actual internal testing process takes a fraction of a second which reduces the likeliness of damaging the DUT, and the robust electronics of our design prevent user error from affecting the tester's circuitry.
Documentation
The documents throughout our project served as a support system to keep the team focused as well as to provide information for individuals not involved in the project. Starting with the Functional Specifications we clearly defined our project by gathering requirements and setting definitive design specifications. Then the Project Plan was created to divide project into a timeline of tasks and major milestones, and within each task we estimated the length of time it would take to complete each one. This would serve as a "to do list" which we could gage our progress and make sure we were meeting our set deadlines. Finally, we created the Theory of Operations. This document provides conceptual documentation how the device functions so that individuals and groups in the future will be able to understand how our device works.
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Chapter / Results5
Technical
General Description
Figure 1 shows the primary components of the 7400 series logic tester and the manner in which they connect to each other.
Figure 1. High-Level System Block Diagram
The process of testing a TTL 7400 series logic chip starts by placing the DUT in the 14-pin ZIF socket. The user continues by selecting the chip type from the menu located on the LCD screen using the keypad. The user then initiates the test by depressing the test key. The testing begins and the PIC microcontroller sends test vectors, which are decoded in the VLSI chip to the DUT. The output of the DUT is sent back to the VLSI chip, and encoded, then sent to the PIC microcontroller for analysis. The user is notified through red and green light emitting diodes (LEDs) whether or not the chip passes the test vectors. Finally the user is allowed the option to continue testing the same chip type or exiting to the main menu to choose another chip type to test.
Hardware Architecture
During this section, the major blocks of the hardware system are described. The sections are: the VLSI chip, PIC microcontroller, user interface architecture, device under test, and power supply.
VLSI Chip
The VLSI chip contains the pin electronics that interface the device under test (DUT) with the PIC microcontroller. The PIC microcontroller’s test vectors are decoded within the VLSI chip and applied to the proper pins of the DUT. The outputs of the DUT are then encoded through the pin electronics of the VLSI chip to the I/O pins of the PIC microcontroller.
PIC Microcontroller
The PIC microcontroller is programmed via assembly code to manage the entire system. The memory of the microcontroller contains chip specific test vectors for the DUT. The DUT is selected through the PIC’s user interface, once selected, the test vectors are sent through the VLSI chip.
User Interface Architecture
The LCD displays the user interface menus, including chips available to test. The LCD screen also displays a message indicating whether the DUT is functioning or malfunctioning. The LCD is controlled by the PIC microcontroller and interfaces with the user by means of the keypad.
The keypad is used to select which TTL device will be the DUT. This allows the PIC to select the correct test vectors to send through the pin electronics. It is also used to start the testing process.
The red and green LEDs indicate whether or not the DUT is functioning properly. Red indicates a malfunctioning chip and green indicates a functioning chip. The LEDs also indicate when the DUT is being tested. The testing process means that the DUT is powered and test vectors are being sent or received. The test status is indicated by both LEDs being lit. During this time the DUT should not be touched.
Device Under Test (DUT)
The DUT is the 7400 Series TTL logic chip the user wants to test. This can be one of ten pre-selected chips. The DUT plugs into a twenty-pin ZIF socket.
Power Supply
A five-volt DC power supply with a three-ampere current rating is used to power the system.
Software Architecture
The descriptions of the major elements of the PIC program architecture of Figure 2 are: the initialization, user menu / wait state, device under test routine, and the testing routine.
Figure 2 provides a top down illustration of the PIC program architecture.
Figure 2. PIC Program Architecture
Initialization
The initialization process sets up the PIC microcontroller and sets the pin electronics to a known state. Initializing the PIC consists of setting the PIC’s pins to be input or output pins for the LCD controller, keypad, VLSI chip and LEDs. It will also initialize the LCD controller. To put the pin electronics in a known state it will reset all of the D flip-flops.
User Menu / Wait State
The user menu displays a list of the available chips to test and waits for user input via the keypad. Depending on the user input it will branch to the appropriate code for that device. The program loops in this state until an input is chosen.
DUT Routine
The DUT routine will wait for the user input to start the testing or go back to the user menu. Once testing begins it will set the register to the appropriate part of memory containing the test vectors and branch to the testing routine. Once the testing routine is finished it will give the option to test a chip again or go back to the user menu.