Preparation of Papers for JLINS 2010 Proceedings (IEEE Format)

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Preparation of Papers for JLINS’2010 Proceedings (IEEE Format)

First Author, Second Author and Third Author

Abstract—A low-noise and high-bandwidth Transimpedance Amplifier (TIA) at 2.75 GHz has been implemented in 0.35 μm CMOS technology. The designed amplifier is configured on three identical stages that use an active load. This structure operates at 3.3V power supply voltage, displays a transimpedance gain of 531 Ω, exhibits a gain bandwidth product (GBW) of 1.46 THzΩ and a low-noise level of about 12.8, while operating with a photodiode capacitance of 0.4 pF. The predicted performance is verified using simulations tools with 0.35 μm CMOS AMS parameters.

Index Terms—Receiver, CMOS Technology, Layout.

I.Introduction

I

Tis challenging to design a good current to voltage (transimpedance) amplifier for high transfer rate optical transmission, such as LAN (Local Area Networks) and FTTH (Fiber-To-The-Home). The performance of the optical interconnection system depends on the receiver’s gain, bandwidth, power consumption, and noise. These four parameters tend to trade-off with each other [1]. The front-end component of typical optical receiver generally is a Voltage-Feedback Amplifier (VFA). The typical amplifier generally requires a low-noise characteristic in order to achieve a good noise figure performance and should operate as high dynamics against the input signal. To meet the noise requirement, two different types of amplifier architectures are proposed [2]. The firstone is a low noise amplifier with high input impedance witch can provide lower noise, but bandwidth can be reduced significantly due to the longer input RC time constant. The second one, so calledthe transimpedance amplifier (TIA) use a resistive shunt-shunt feedback (Fig. 1.), where CPD, CS, and CGare respectively the photodiode, parasitic and gate capacitances that represent the total capacitance at the input (CT). Instead of HIA, the TIA has more noise due to feedback resistance but a wide bandwidth and the designing circuit is simpler. Furthermore, it has a wide dynamic range due to the higher saturation limit and it will be a good architecture for optical receiver systems.

The bandwidth can be improved by increasing the open loop gain of the amplifier, whereas when transmission speed is increased, the number of stages composing the amplifier as well as its open loop gain is necessarily reduced [3]. The TIA must be designed carefully to avoid stability problems associated to systems with negativefeedback[3].

Though the traditional TIA is designed using more expensive IC technologies such as silicon bipolar or GaAs MESFET, there has been an increasing interests in CMOS based implementation because of the demand for the lower cost and greater integration with digital circuits.

II. Design of The Transimpedance Amplifier

A push pull inverter at the input is used to maximize the transconductance of the amplifier and increases its gain bandwidth product (GBP) [4,8]. An improved one stage CMOS implementation of the TIA is presented in Fig.2.

Fig.1. Model of a closed loop TIAwith photodiode

Fig. 2. The proposed CMOS TIA circuit

The TIA takes a current from the input and converts it into a voltage signal. The transistors M1 and M3 form the inverter while M2is added to increase the bandwidth and minimize the Miller effect. To design such an amplifier, by knowing that the gain can be approximated by the value of the feedback resistor, we evaluate RF while estimating CT. These two parameters will be used as starting point in the design. The gain of the inverter will be exploited in addition to the negative feedback, which will impose an increase in the gain. Thus, from the small signal model, the expression of the gain will be,

(1)

The cut-off frequency at 3 dB is increased by the transconductance of M2 as long as the gain is simultaneously reduced. The signal should be amplified through subsequent amplifiers because of the low-gain of the single amplifier stage. Then, we will have,

(2)

where : et

The complete improved transimpedance amplifier (Fig. 3.) consists of three identical cascaded stages. We can use a resistor as a feedback or a PMOS transistor as an active feedback resistor biased by the voltage source VG[4,5]. The feedback resistor will be determined using,

(3)

With taking into account the Miller Effect, the bandwidth of the transimpedance is approximately equal to,

(4)

Where AG is the total gain of the tree stages witch is equal tocubic open loop gainAOL. The stability of the system is related to A, and the total gainA of the system must be strictly controlled.

A conceptual optimization has been considered by taking the gain of a single stage of the TIA. An analysis has been carried out by introducing the different intrinsic capacitances at the level of each MOS transistor Fig.4.

By taking C1 and C2, the capacitances at nodes (1) and (2) respectively, the cut-off frequency of the single amplifier in the open loop configuration at node (2) is given by,

Fig.3. The proposed TIA with three identical cascaded stages

Fig.4. Capacitances involved in one amplifier stage

(5)

By using Eq. 1, the cut-off frequency at node (2) will be expressed as follow,

(6)

The gain bandwidth (GBP) product of the single-stage amplifier will be,

(7)

and considering C2 = m.C1, we get,

(8)

where f0 is the cut-off frequency at node (1).

The frequency f1 determines the second pole. To ensure good stability, this pole must be located beyond the dominant pole according to the following condition [5],

(9)

where is a factor ranging between 2 and 3 [5]. Under these conditions AOL will be expressed as follows,

(10)

In our case, the transimpedance structure consists of three identical stages in cascade. Therefore, in the node (2) the capacitance C1 is added and we obtain,

(11)

The gain bandwidth product of each stage will be,

(12)

To obtain the same phase margin as for a single stage, the cutoff frequency of each stage will be equal to [6]:

(13)

where n represents the number of stages and f3ithe cutoff frequency of the transimpedance structure. The gain of each stage of our structure has the following expression,

(14)

which gives,

(15)

Knowing (the PMOS/NMOS mobility ratio of the Push-Pull inverter), the use of the term giving the open-loop gain of a single stage in the dimensions of the transistors, we can evaluate the term gm1+gm3and the various capacitances depending on the gain.Indeed, from Eq.2 and using that giving , we estimate the lower limits of the dimensions of the transistors constituting the inverter Push-Pull. After development, we get,

(16)

and,

(17)

To have the widest bandwidth possible, the transistor constituting the charge must has the smallest size possible. This requires us to choose Wn2 in the limit of 0.35µm process technology.

The TIA uses a negative feedback to obtain a stable transimpedance gain and a large bandwidth, but this negative feedback can cause stability problems. A compromise was already mentioned between the bandwidth and the gain because it is known that increasing bandwidth adversely affects the gain and vice versa, so in first place we decreased the gain by playing with the parameters of the feedback transistor by increasing its width and decreasing its bias voltage Vg (which provides a low resistance). We thought it was sufficient but the simulation results have shown the presence of a peak in the gain curve witch can gives instability.Forhigh-frequency applications, the dominant pole of the open loop frequency response is located at the input node, while the no dominant poles are those of the amplifier. The poles of the amplifier can be located at high frequencies, preferably above the cut-off frequency f−3dB, to ensure good stability. Therefore, amplifier stages with low gains and large bandwidths should be used. The localization of the amplifier poles can be designed to yield a stable response [5].

After locating the other pole of the amplifier we started to increase the width of the two transistors Wn1and Wp (which are proportional to the cutoff frequencyf-3db) to remove it from the critical point.

We used a photodiode with capacitance of 0.4pF, also we estimated the total capacitance at 1pF including parasitic capacitance and the capacitance at the input node. So by using Eq.3, Eq.4, and Eq.15, the estimated equivalent feedback resistor is 531 Ω, and the 3 dB bandwidth equal to 2.75 GHz.

II.Noise Analysis

The equivalent noise power at the input node is given by Eq.18[4]. Where q is the electron charge, k is Boltzmann’s constant, T is the absolute temperature, Idarkis the dark current of the photo detector, IGis the gate current,CT is the total input capacitance, Rin the input impedanceand B indicates the useful bandwidth. If we use a PMOS transistor as a feedback we eliminate the factor 4kTB/RF. Thus,

(18)

The last term is the more prominent then the noise power, depends mainly on B3 and . This last term gives the absolute minimum noise that can occur at the input, assuming RFextremely high. However, the noise performance is close to the optimum when [7],

(19)

An increase in the capacitance (CGS + βCGD) in extreme lower cases enables us to carry out this optimization. This is obtained with a definite number M of transistors connected in parallel. Thus, the capacitance of the transistors of attack will be equal to Mx(CGS+βCGD), the total transconductance however, will be equal to Mgm. This allows us to assess CGS, CGD, and gm translated by their respective relationship. In assessing Mx(CGS+βCGD) at around the minimumvalue (so that CT =CPD+CS+Mx(CGS+βCGD)= 1pF). Thus the value of M is given by the following equation [3]:

(20)

where δ is a factor which reflects the inequality given in Eq. 19, it varies between 0.1 and 2.0, while respecting the following constraints,

(21)

The introduction of a PMOS transistor connected in resistance reduces the noise level of this structure transimpedance. In addition to this advantage it reduced considerably the surface during the integration of the active resistance, carried out in poly, take a place in the chip. Thus, this structure keeps the same performance as with resistance.

III.Simulation Results

The TIA shown in Fig.1 is implemented with 0.35μm CMOS technology, and the power dissipation is 53.5mW with 3.3V supply voltage. The Layout of the chip is shown in Fig. 5.We obtain a chip size of about 1252 µm2.Fig.6 shows the gain versus frequency response of the TIA. As it is shown in Fig.6, the transimpedance gain is about 531Ω and the bandwidth is 2.75GHz, which makes the amplifier suitable for speed up to 5Gb/sin optoelectronics application. The simulated noise at the input of the proposed topology is depicted in Fig. 7, which shows a maximum at low frequencies, then it falls and tends to zero at high frequencies along the desired frequency range.

A DC analysis giving the output voltage versus the photocurrent is shown in Fig. 8. This characteristic shows a good linearity of the amplifier as well as a high dynamic range along a high input current range.

The output signal shown in Fig.9 is apulse signal generated by the application of a pulse photocurrent signal. It ensures a correct transfer rate of the designed TIA.

IV.Conclusion

A low noise and high bandwidth TIAhas been designed and simulated in a standard 0.35 µm technology, The proposed TIA achieve 2.75GHz3 dB bandwidth, 54.5 dBΩ transimpedance gain, with 53.5mW of power dissipation from a 3.3 V supply voltage.

The analytical illustrations as well as different simulation results given by PSpice tool show that the designed amplifier displays good optimized performances that offers considerable gain, good dynamic range and, particularly a relatively low-noise level at the input.

These performances are required in most communication standards, which make the TIA more feasible to achieve a higher transmission speed. Table.3. summarizes the results of designed TIA and gives different results in comparison to previous works.

Fig. 5. Layout of the whole TIA

Fig.6 . Transimpedance gain (I-V gain) versus frequency

Fig.7. Input noise current of the whole TIA

Fig. 8.Output voltage versus Input photo-current

Fig. 9. Pulse response of the whole TIA

TABLE. I.

Performances summary of the proposed TIA:

Comparison with others works.*This Work

Ref. / Tech. / CPD
(pF) / BP
(GHz) / Gain
(dB.Ω) / Noise
() / Power
(mW)
[9] / 0.35 µm / 1.5 / 1.90 / 65.0 / 9.7 / 17 (3.3V)
[10] / 0.50 µm / 0.6 / 1.20 / 64.0 / 0.6 / 115 (3.3V)
[11] / 0.18 µm / 0.2 / 1.80 / 58.7 / 13.0 / 47 (31.8V)

Acknowledgment

This work was supported by MESRS (Ministère de l’Enseignement Supérieure et de la Recherche Scientifique) under the supervising of the CNEPRU,

References

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Manuscript received January 25, 2010. This work was supported in part by the MESRS Ministry under Grant J0200220090020. First Author is with the Laboratory of Instrumentation, USTHB, PO.Box. 32, Bab-Ezzouar, Algies, Phone: 213-24217912 (Ext. 804), Fax: 213-21207664, URL: Email: . Second Author is also with the Laboratory of Instrumentation, USTHB, PO.Box.32, Bab-Ezzouar, Algies.