H. JONATHAN CHAO
Polytechnic Institute of New York University
5 Metrotech Center, Brooklyn, NY 11201
Tel: 718-260-3302 (work)
Tel: 732-687-4949 (cell)
Email:
URL: eeweb.poly.edu/~chao
EDUCATION
· Ph.D in Electrical Engineering, The Ohio State University, Columbus, 5/85.
· M.S.E.E, National Chiao Tung University, Taiwan, ROC, 5/80.
· B.S.E.E, National Chiao Tung University, Taiwan, ROC, 5/77.
PROFESSIONAL EXPERIENCE
· Polytechnic Institute of New York University, Dept. of Electrical and Computer Engineering, Brooklyn, NY
Department Head: 7/04 – present
Full Professor: 9/97 – present
Associate Professor: 1/92 – 8/97
Three of my research projects are briefly described below:
1. Network Security: We are designing and implementing high-speed network security functions, including intrusion detection/prevention and distributed denial of service (DDoS) defense systems, on FPGA boards with a target rate of 10 Gbps and beyond.
2. Ultra-Large Scalable Packet Switches: We designed an electronic packet switch scalable to 40 terabit/s. A small-scale switch was prototyped with FPAG chips on several printed circuit boards (funded by NSF). We are currently investigating optimum high-performance packet scheduling that can achieve the best packet delay performance, even better than the maximum weight matching scheme, traditionally thought the best scheme (currently funded by NSF).
3. Photonic Packet Switches: We prototyped an optically transparent WDM ATM Multicast (3M) switch with University of Maryland at Baltimore County, which was a 6-year project funded by DARPA.
Courses that I have taught at Polytechnic University:
1. Advanced Network Security: Architectures, Algorithms, and Implementations (EL6393)
2. High-Speed Networks (EL6383), used the QoS Control book I co-authored for the textbook
3. High-Performance Switches and Routers (EL7373), used the switches/routers book I co-authored for the textbook
4. Integrated Circuit (VLSI) Design (EL547)
5. VLSI System and Architecture Designs (EL644)
· Coree Networks, Inc., Tinton Falls, New Jersey, CTO and Founder: 7/00 – 8/01
o Took one-year leave of absence from Polytechnic University to start up the company with the first round of $30M venture capital fund. The company closed down in a little over a year due to the downturn of telecom market. It had 95 employees when closing down.
o Oversaw all research and development activities related to Coree’s product line and explored new technologies for terabit IP routers and MPLS switches.
o Led a team to design a fault-tolerant packet switch system with more than 10 terabit/s capacity and five 9 availability, including the design and modeling of 3 ASIC and 8 FPGA chips.
o Led a team to investigate different layers of protection/restoration and traffic engineering in the IP/MPLS network.
· Consultant to Telcordia, NEC, and Lucent at various times during 1/92 – 6/00
· Telcordia (Bellcore), Red Bank, New Jersey, Member of Technical Staff, 5/85 - 1/92
Involved in the following projects:
1. ATM Congestion Control
Implemented a VLSI chip (150 thousand CMOS transistors), called a Sequencer, to shape user traffic from thousands of virtual channels in ATM networks. The chip also facilitates a queue manager that handles multiple delay and loss priorities jointly in ATM switch nodes. The chip has been used in the Aurora Gigabit testbed (by Bellcore, IBM, MIT and University of Pennsylvania).
2. Nectar Gigabit Network Testbed Project
Played a key role in designing an architecture for interconnecting gigabit hosts/LANs through SONET/ATM networks, converting HIPPI (High Performance Parallel Interface) packets at Gbit/sec to the SONET/ATM transmission format, and vice versa.
3. A Large-Scale Modular ATM Switch
The proposed ATM switch uses a regular and recursive structure to accommodate thousands of input ports, resulting in a capacity over 1 Terabit/sec.
4. A SONET/ATM-based Optical Customer Premises Network
A new optical customer premises network, called H-Bus, was designed to interface multiple terminal equipment to an ATM network. To resolve the access contention on the bus, a new multiple-priority media access control (MAC) protocol was devised and implemented with a 1.2-mm CMOS VLSI chip, called an ATM-Layer chip.
5. A Packet Video/Audio Transmission System
Prototyped a point-to-point packet transmission system, which statistically multiplexes a video signal and two audio channels. A novel digital phase-locked loop circuit was implemented to recover the service clock that is not carried by the packet network.
6. A 200 Mbit/s Framer Chip for a B-ISDN System
Implemented a 2-mm CMOS LSI chip, called a Framer, to support a SONET-like time division multiplexer. Several hundreds of the chip were fabricated and used in trial systems by Regional Bell Companies.
7. A 2-mm CMOS Regenerative Phase Aligner Chip
Implemented a 120 Mbit/s Regenerative Phase Aligner (REPA) chip to align the phase of a high-speed data stream to a local system clock.
· Polytechnic University, Dept. of Electrical Engineering, Brooklyn, NY
Adjunct Associate Professor, 9/85 - 12/91
Developed and taught two courses:
o Integrated Circuit (VLSI) Design (Basics)
o VLSI System and Architecture Designs (Advanced)
· Telecommunication Laboratory, Taiwan, Senior Engineer, 9/77 - 9/81
Designed a fault-tolerant microcomputer controller of a local digital switching system;
involved in designing and implementing a time-space-time digital switching system.
SERVICES IN UNIVERSITY
1. Chair of Undergraduate Computer Engineering Steering Committee (since 1993) with responsibility of Computer Engineering curriculum and coordination between ECE and Computer Science departments.
2. Chair of ECE Dept Tenure and Appointment Committee.
3. Member of University Tenure and Appointment Committee.
4. Member of University Undergraduate Curriculum Standards Committee.
5. Advise MS Computer Engineering students on their curriculum and handling their admission.
PROFESSIONAL ACTIVITIES
1. Have been serving as Panelist for NSF proposals.
2. Editor of IEEE/ACM Trans. on Networking from Aug. 1996 to Sep. 2000.
3. Guest editor of IEEE Journal on Selected Areas in Communications with special topic on “High-Speed Network Security – Architectures, Algorithms, and Implementations” for Oct. 2006 issue.
4. Guest editor of IEEE Journal on Selected Areas in Communications with special topic on “High-Performance Optical/Electronic Switches/Routers for High-Speed Internet” for May and September issues of 2003.
5. Guest editor of IEEE Journal on Selected Areas in Communications with special topic on “Next Generation IP Switches and Routers” published in June 1999.
6. Guest editor of IEEE Journal on Selected Areas in Communications with special topic on “Advances in ATM Switching Systems for B-ISDN,” published in June 1997.
7. TPC member of a number of conferences, such as HPSR (High-Performance Switching and Routing), ICC, Globecom, and etc.
INVITED SHORT-COURSES
1. Have given a 3 or 4-day short course several times a year to industry worldwide through the arrangement of UC Berkeley and Oxford University Continuing Education Division for more than 10 years until year 2002. The titles of the short courses are “SONET/ATM Networks” and “IP/MPLS Networks.”
2. Three-day short course, “VLSI Designs for Broadband ISDN,” National Chiao Tung University, Taiwan, July 1988.
HONORS AND AWARDS
1. Elected to be Speaker of the Year by IEEE New Jersey Coast Section, April 2003.
2. Elected to be Fellow of IEEE for contributions to the architecture and application of VLSI circuits in high-speed packet networks in January 2001.
3. Co-recipient of the journal's best paper award of 2001 IEEE Transactions on Circuits and Systems for Video Technology.
4. Received Bellcore Excellence Award in March 1987 for designing the first SONET-like Frame chip running up to 200 Mbit/s using CMOS 2-mm technology.
BOOKS
1. Broadband Packet Switching Technologies – A Practical Guide to ATM Switches and IP Routers, H. J. Chao, C. Lam, and E. Oki, published by John Wiley & Sons, Inc, in Sep. 2001.
2. Quality of Service Control in High-Speed Networks, H. J. Chao and X. Guo, published by John Wiley & Sons, Inc, in Nov. 2001.
3. High Performance Switches and Routers, H. J. Chao and B. Liu, published by John Wiley & Sons, Inc, in April 2007.
PATENTS
1. M. Beckner, H. J. Chao, and T. Robe, “Framer circuit for use in DTDM (Dynamic Time-Division Multiplexing) network,” patent no. 4,819,226, Apr. 1989.
2. H. J. Chao and S. Lee, “Time division multiplexer for DTDM bit streams,” patent no. 4,833,673, May 1989.
3. H. J. Chao, “DTDM multiplexer with cross-point switch,” patent no. 4,855,999, Aug. 1989.
4. H. J. Chao, S. Lee, and L. Wu, “Method and apparatus for multiplexing circuit and packet traffic,” patent no. 4,893,306, Jan. 1990.
5. H. J. Chao and C. Johnston, “Service clock recovery circuit,” patent no. 5,007,070, Apr. 1991.
6. H. J. Chao, G. Shtirmer, and L. S. Smoot, “Optical customer premises network,” patent no. 5,050,164, Sep. 1991.
7. H. J. Chao, G. Shtirmer, and L. S. Smoot, “Customer premises network node access protocol,” patent no. 5,079,763, Jan. 1992.
8. H. J. Chao, “Grouping network based non-buffer statistical multiplexer,” patent no. 5,124,978, June 1992.
9. H. J. Chao, “Crosspoint matrix switching element for a packet switch,” patent no. 5,179,552, Jan. 1993.
10. H. J. Chao, “Distributed modular packet switch employing recursive partitioning,” patent no. 5,197,064, Mar. 1993. This patent has been licensed to AT&T.
11. H. J. Chao and C. Johnston, “Service clock recovery for variable bit rate services,” patent no. 5,204,882, Apr. 1993. This patent has been licensed to AT&T.
12. H. J. Chao, “Method and system for managing queued cells,” patent no. 5,278,828, Jan. 1994. This patent has been licensed to AT&T.
13. H. J. Chao, “B-ISDN Sequencer chip device,” patent no. 5,313,579, May 1994.
14. H. J. Chao, “Method and system for controlling user traffic to a fast packet switching system,” patent no. 5,381,407, Jan. 1995.
15. H. J. Chao and B. S. Choe, “Scalable multicast ATM switch,” patent no. 5,724,351, March 1998.
16. H. J. Chao and N. Uzun, “ASIC chip for implementing a scalable multicast ATM switch,” patent no. 5,790,539, Aug. 1998.
17. H. J. Chao and X. Guo, “Methods and apparatus for handling time stamp aging,” patent no. 6,081,507, June 2000.
18. H. J. Chao and Y. R. Jenq, “Methods and apparatus for shaping queued packets using a two-dimensional RAM-based search engine,” patent no. 6,370,144, April 9, 2002.
19. H. J. Chao and Y. R. Jenq, “Methods and apparatus for fairly scheduling queued packets using a RAM-based search engine,” patent no. 6,389,031, May 14, 2002.
20. H. J. Chao and A. Altinordu, “Methods and apparatus for providing a fast ring reservation arbitration,” patent no. 6,449,283, Sep. 10, 2002.
21. H. J. Chao, “Methods and apparatus for fairly arbitrating contention for an output port,” patent no. 6, 487, 213, Nov. 26, 2002.
22. H. J. Chao and J. S. Park, “Methods and apparatus for arbitrating output port contention in a switch having virtual output queueing,” patent no. 6,667,984, Dec. 23 2003.
23. H. J. Chao and E. Oki, “Scheduling the dispatch of cells in multistage switches using a hierarchical arbitration scheme for matching non-empty virtual output queues of a module with outgoing links of the module,” patent no. 7,103,056, filed on June 1, 2001, awarded September 5, 2006.
24. H. J. Chao and E. Oki, “Scheduling the dispatch of cells in multistage switches,” patent no. 7,173,931, filed on May 8, 2001, awarded Feb. 6, 2007.
25. H. J. Chao, E. Oki, and R. Rojas-Cessa, “Pipelined maximal-sized matching cell dispatch scheduling,” patent no. 7,006,514, filed on June 1, 2001, awarded Feb. 28, 2006.
26. H. J. Chao, E. Oki, and R. Rojas-Cessa, “Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme,” patent no. 6,940,851, filed on July 23, 2001, awarded Sep. 6, 2005.
27. H. J. Chao, E. Oki, and R. Rojas-Cessa, “Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme,” patent no. 7,046,661, filed on July 23, 2001, awarded May 16, 2006.
28. H. J. Chao, Y. Li, and S. S. Panwar, “Arbitration using dual round robin with exhaustive service of winning virtual output queue,” patent no. 7,203,202, file on Oct. 31, 2002, awarded April 10, 2007.
29. W. Lau, M. C. Chuah, Y. Kim, and H. J. Chao, “Distributed architecture for statistical overload control against distributed denial of service attacks,” filed on Nov. 26, 2003.
30. H. J. Chao and J. S. Park, “Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch,” filed on Feb. 11, 2004.
31. H. J. Chao and J. S. Park, “Switch module memory structure and per-destination queue flow control for use in a packet switch,” filed on Feb. 11, 2004.
32. H. J. Chao and J. S. Park, “Packet reassembly and deadlock avoidance for use in a packet switch,” file on June 18, 2004.
33. H. J. Chao and J. S. Park, “Packet-level multicasting,” filed on June 18, 2004.
34. H. J. Chao and J. S. Park, “Maintaining packet sequence using cell flow control,” file on Dec. 3, 2004.
35. H. J. Chao and H. Sun, “Providing a high-speed defense against distributed denial of service (DDoS) attacks,” filed on June 6, 2006.
36. H. J. Chao and K. Xi, “Determining rerouting information for single-link failure recovery in an Internet protocol network,” filed on April 10, 2007.
37. H. J. Chao and K. Xi, “Determining rerouting information for single-node failure recovery in an Internet protocol network,” filed on April 10, 2007.
38. S. Artan and H. J. Chao, “Generating a hierarchical data structure associated with a plurality of known arbitrary-length bit strings used for detecting whether an arbitrary-length bit string input matches one of a plurality of known arbitrary-length bit strings,” filed on October 26, 2007.
39. S. Artan and H. J. Chao, “Detecting whether an arbitrary-length bit string input matches one of a plurality of known arbitrary-length bit strings using a hierarchical data structure,” filed on October 26, 2007.
40. H. J. Chao and K. Xi, “Determining rerouting information for double-link failure recovery in an Internet protocol network,” filed on Nov. 2, 2007.
41. H. J. Chao and K. Xi, “Rerouting for double-link failure recovery in an Internet protocol network,” filed on Nov. 2, 2007.
42. H. J. Chao, S. S. Panwar, and Y. Shen, “Providing 100 Percent Throughput in a buffered crossbar switch,” filed on Dec. 31, 2007.
43. S. Artan and H. J. Chao, “Generating a boundary hash-based hierarchical data structure associated with a plurality of known arbitrary-length bit strings and using the generated hierarchical data structure for detecting whether an arbitrary-length string input matches one of a plurality of known arbitrary-length bit strings,” filed on Feb. 5, 2009.