PLL LAB
PHASE-LOCKED LOOP FM DEMODULATOR
CIRCUIT DIAGRAM
NAME / CAR. FREQ. / FMCARRIER PEAKFREQ.DEV / SUPPLY VOLTAGES / DEMOD. O/P / DEMOD.BANDWIDTH
(Hz) / (Hz) / (VP) / (Hz)
1 / 50000 / 3000 / ±6V / 2 / 2000
2 / 55000 / 3250 / ±7V / 2.5 / 2000
3 / 60000 / 3500 / ±8V / 3 / 2000
4 / 65000 / 3750 / ±9V / 3.5 / 2000
5 / ADRIANO, ROBERT / 70000 / 4000 / ±10V / 4 / 2000
6 / AMARO, ANDREW / 75000 / 4250 / ±6V / 2 / 2000
7 / BELSHER, CLINTON / 80000 / 4500 / ±7V / 2.5 / 2000
8 / CANTUSCI, FRANCO / 85000 / 4750 / ±8V / 3 / 2000
9 / CARTY, MATTHEW / 90000 / 5000 / ±9V / 3.5 / 2000
10 / CHANA, TEJPAL / 95000 / 5250 / ±10V / 4 / 2000
11 / DACCACHE, ELIE / 50000 / 3000 / ±6V / 2 / 3000
12 / DEGROOT, NATHAN / 55000 / 3250 / ±7V / 2.5 / 3000
13 / GENEREUX, CHRIS / 60000 / 3500 / ±8V / 3 / 3000
14 / HAMILTON, SEAN / 65000 / 3750 / ±9V / 3.5 / 3000
15 / MCGRATH, JEFFREY / 70000 / 4000 / ±10V / 4 / 3000
16 / MEI, MARK / 75000 / 4250 / ±6V / 2 / 3000
17 / MIGDAL, ROBERT / 80000 / 4500 / ±7V / 2.5 / 3000
18 / MISSIOS, MARIA / 85000 / 4750 / ±8V / 3 / 3000
19 / ROBINSON, JAMES / 90000 / 5000 / ±9V / 3.5 / 3000
20 / SCHONBERG, RYAN / 95000 / 5250 / ±10V / 4 / 3000
21 / SLEIMAN, FIRASS / 100000 / 5500 / ±6V / 2 / 3000
22 / TRAN, DUY / 105000 / 5750 / ±7V / 2.5 / 3000
PRE-LAB
1.Design a third order FM demodulator with a BESSEL gain response that meets your assigned case specifications. Use the LM565 as the PLL and LM301 op amps to allow input voltages right up to the positive supply voltage. Show all component values directly on the circuit diagram for your pre-lab submission. AC couple the input signal and design the input circuit for an input resistance of 1k. Do not forget to use a compensation capacitor with LM301 op amps to stabilise them.
2.Calculate the expected lock range, capture range, and sketch the demodulator gain response (Vout/in versus FMOD) showing all relevant parameters (LF gain, cutoff frequency, attenuation rate).
3.Calculate the expected demodulated voltage VC1 and the % ripple of VC1 and VDEMOD.
4.Calculate the maximum peak phase error assuming sinewave modulation..
PROCEDURE
1.Lock range
Open file PLL-FM-DEMOD-LOCK-RANGE and edit the system parameters to model your own PLL. Measure lock range by using a ramp signal as the input frequency (in r/s) – display Vdemod, in, vco and e simultaneously. Start the input frequency ramp inside the lock range at cen with a slow enough rate and ramp up to max. Re-do for min by ramping in down.
2.Capture range
Open file PLL-FM-DEMOD-CAP-RANGE and edit the system parameters to model your own PLL. Measure capture range by using a ramp signal as the input frequency (in r/s) – display Vdemod, in, vco and e simultaneously. Start the input frequency ramp outside the capture range, below min and ramp in up at slow rate and until capture occurs. Re-do for max by ramping in down.
3.Capture Time
Open file PLL-FM-DEMOD-Tcap and measure capture time for two different input frequencies, one that is 15% away from Fcen and another that is 20% away from Fcen. Display Vdemod, in, vco and e simultaneously. Verify that Fdemod = Fin – Fvco when PLL is not locked.
4.Demodulation of sinusoidal modulation signal
Open file PLL-FM-DEMOD-sine and use sinewave modulation with proper amplitude to produce the maximum FM frequency deviation you have been assigned and a mod frequency of 100 Hz:
A)measure the minimum , maximum and average phase error.
B)measure the LF and HF AC components of the demodulated output. % ripple =?
C)measure the LF and HF AC components of Vc (pin#7)
D)measure the LF and HF AC components of VC2. % ripple =?
E)measure the minimum and maximum duty cycle of Vdet (detector O/P)
F)Increase the modulation signal amplitude enough the cause the PLL to unlock and observe all the waveforms, especially the phase error waveform and explain what happens.
G)Determine the maximum frequency deviation just before the PLL unlocks for the following modulation frtequencies: Fmod = 0.1 Fn1, 0.5 Fn1, Fn1, and 2 Fn1 where Fn1 is Fn of the PLL. Simulate the results and explain.
Demodulator bandwidth measurement
You cannot use the Bode plot feature to simulate the frequency response of the system because it contains non-linear elements and Systemview linearises them when it does a Bode plot and this produces the wrong frequency response.
Open file PLL-FM-DEMOD-FRESP and adjusts the ramp rate set for mod and the simulation time to cover a range of 0 to 1.5 BW. Run the simulation and observe the final Vdemod and mod and read the mod value at which Vdemod is down by 3 dB (or 70.7%) - this is the demodulator BW.
5.Demodulation of sinusoidal modulation signal
Open file PLL-FM-DEMOD-square and measure the transient response of VC2 and of the demod O/P. Measure % overshoot using to a 100 Hz squarewave. And calculate of PLL from overshoot of VC2. Why is overshoot of demod O/P so small?
POST LAB
Include all simulation waveforms in report. Compare all simulation results to your predictions and explain the results in terms of the operation of the PLL.
Rev. 10/8/2018 Phase-Locked Loop LAB Page 1