PAF Planning Meeting

Location: Charlottesville

Date: 2014-02-06

Attending: Bill Shillue, Rick Fisher, Matt Morgan, Steve White, Bob Simon, Morgan Mcleod

Agenda

Prior to the Meeting Bill sent a rough agenda by email as follows:

LNA amplifier performance and devices: I would like for us all to compare notes on the amplifier issues that we saw, and formulate a reply to Sandy’s emails from November.
LNA new design – way forward on this, design with bare transistors, what is our stock?, should we consider buying new device from Sandy (lower noise than DigiKey but likely we’ll see failures again, ..
Production of 40 new LNAs for FLAG PAF: plan for design, assembly, test
Beyond that, where will we get our devices?
Noise temperature measurements : Steve summarizes the noise temperature measurements from OTF in Dec., what we did to optimize for noise and dynamic range, … is there more to be done?
Bead cracking problem: discussion on how to address this
Further FLAG PAF testing: I think we are waiting to see some early results of prior measurement. Should I see if we can get GBT time in Spring, ..is it worth measuring with the GBT2 dipoles? Can we gain anything from using BYU 20 MHZ backend?
A look at the GBT data: (Rick)
New ideas for nextgen PAFs (Rick)…group brainstorming
Digital downconverter Status (Matt)
Digital downconverter interfaces: power, Ethernet, …etc
Plan for backend for digital downconverter discussion

LNA Discussion

It was agreed that we would pursue immediately a new LNA design based on the bare transistors in-hand. There was consensus to avoid plastic packages altogether. So that leaves us with a short term solution (bare transistor) but needing a new supply of low noise devices for the long term. Bill will start this with Matt consulting, and for now the assembly and testing is an open question. Steve advised that GB can do either but the question will be throughput. On the question of new devices, it was agreed that we would start by talking more to JPL.

It was also agreed to make a response to JPL about our experience with the SiGe LNA design with plastic packages as Sandy has requested. Bob will collect as much data on this as he can, and attept an I-V measurement if there are intact failed devices. Steve reported that the failures sometimes appeared to occur in stages, first with a decrease in gain, then working only at warm temperatures, then possibly with a total failure. ESD has not been ruled out as a failure cause. Matt suggested the use of an ESD discharge resistor and abandoning the use of plastic packages.

The LNA impedance match was discussed, in particular the possibility that we will want to include Z-match in the next iteration. Matt suggested that we proceed with design and leave room on the board for an impedance network. Rick pointed out that the rationale for the Z-match was to allow the element optimization to be for pattern only (not Z).

Matt speculated that a wafer run for bare die transistors could be $100-$200K, and would require new design tools. Possible foundries: IBM, Ga Tech? If you specify the doping profile then you need the full wafer (as opposed to hitching a ride on someone else’s wafer).

On the new LNA design: The first LNA in any case will likely be built in Cvilel by Todd or Waveley. Aluminum bonds to aluminum pads (on the transistor) to ENEPIG on the circuit board. Comment: Rogers 4350 is stiffer than Cuflon, alumina is very expensive.

Digital Downconverter

Matt reports on this. 5 boards, 8 channels per board. Parts ordered, boards fab’d. Wait on chassis, bias connectors, lasers. Todd will assemble, forecast testing at end of March.

Interfaces

Mechanical Fit: this was not discussed much except to agree that there should eb no trouble fitting this into the receiver chassis. This is mechanical fixturing, work TBD.

Size of the electronics is about 4 x 10 x 1.5 inch

Thermal: dissipation expected 175W. allowance for air flow in the box is necessary, and the box is controlled by Peltier elements.

Fiber optic:

Currently the PAF receiver has 48 FC type fiber adapters on the bulkhead. These interface internally to the analog transmitter modules which come out in 3mm ( or 1mm?) jacketed fiber terminated in FC-APC. Externally there is some kind of physical and weather protection (photo form Bob?)

For the DDC, the assemblies have 40 fibers coming out with a termination TBD. There are a few options TBD:

1. Splice on FC-APC just like current setup and keep the receiver connector bulkhead as-is.

2. Splice on ribbon connectors for fewer mating interfaces at the receiver bulkhead

3. Include the DDC in a larger metal box assembly that also could include power supply, splice tray, and/or clock fanout assembly. Make on panel of the box flush with the receiver bulkhead so connection is made directly to the DDC.

external to the receiver there is 48 connectorized SM fiber FC-APC

SteveW mentioned a preference for replacing this with something much easier to connecto/disconnect, possibly a multi fiber connector(s)

Power supplies: Existing receiver power supplies are

Lambda LNS-W-5-0V, linear 5V, rated 14A at 40ºC, measured draw is 7.05A
Power One HB5-3/OVP-A, linear 5V, rated 3A at 40ºC, measured draw is 386mA
Acopian A12H1300, linear 12V, rated 13A at 40ºC, measured draw is 7.13A
Power One HAD15-0.4A, linear +/-15V, rated 0.4A at 40ºC, measured draw is 29mA for +15V, and 144mA for -15V

DDC power requirement as follows: 5 x ( 5V 2.5A, 3.5V 6.4A), also 24V, 150mA fan

Linear DC power supplies are assumed for GB receiver operation

Power connector is micro-D

Monitor and Control:

25 control outputs (5 bits of attenuator setting for each of the 5 downconverter cards) and read at least 120 monitor points (RF input-power and I and Q output-powers for each of 40 channels)

The design provides for all of these M&C to be implemented via SPI bus

Jason Castro has designed an interface board consisting of Rabbit micro with SPI bus driver, written firmware to implement the SPI protocols, and designed a software web interface for testing.

The PAF implementation will require an Ethernet input device with SPI but output to accomplish the M&C for the DDC.

Currently, the PAF receiver has a Netburner interface that could accomplish this. However, new firmware, software and wiring will be needed. The Netburner currently in use is the MOD5282 Ethernet Core Module: http://www.netburner.com/products/core-modules/mod5282

As far as RFI, anything digital like this needs to be in a shielded box, with fully gasketed lid. AC or DC power typically goes through filtered connectors, usually spectrum control. Any copper signal wires in/out would also need filtering. Fiber goes thru a tube operating as waveguide beyond cutoff, or there are metal-ferruled optical connectors which do the same thing.

All equipment that gets installed on the GBT needs tested in our anechoic chamber. The specs for this are a little messy...but basically if there is any detectable RFI, then it fails, and requires additional shielding.

Clock Signal:

155 MHz with fanout five places 0.5 mW minimum, 5 mW nominal

If a 5 or 10 MHZ reference is brought to the receiver, then we require a small ref clock generation module with 5 outputs each locked to the reference

LVDS 100 ohm cable?, connector?

Local Oscillator:

1.3—1.8 GHz nominal -3 dBm SMA input

Backward Compatibility

The installation of the digital downconverter must be done in such a way as to allow backward compatibility for the Beamformer-Backend project (WVU/BYU). This could mean removal of the digital downcopnverter and replace with the analog link assembly. But the fiber connections, DC power, …all interfaces must be backward compatible. An alternative is to assemble the new digital downconveter into a second receiver box and move the front end between them.

Bead Cracking Problem

Bob Simon summarized:

· K-Connector beads had more loss than quartz, leading to the design selection of the quartz bead vacuum feedthrus.

· W-band epoxy was previously used, a clear epoxy with a thin (like water) consistency

· Sliding contact for cold end of center pin

· The bead was set in a small recess but the thickness of the epoxy caused the bead profile to rise above the level of the top of the dewar.

Backend for Digital Downconverter

A new backend is needed to process the larger bandwidth and digital modulation format

2.5 GB/sec , 16 bits at 155 MB/sec, 38 fibers so 608 digital bits at 155 Mbit/sec

Questions:

· How many FFTs can be processed in a single FPGA

· How to get bits into FPGA

· What are the pin counts available on Roach2s

Jason: pincount may be the limiting factor

Appendices

LNA Design Details

Datasheet for BFU725F transistor:

http://www.nxp.com/products/rf/transistors/bipolar/high_linearity_amplifiers_high_output_amplifiers_drivers/6_ghz_gt_12_ghz_x_ku_low_band/BFU725F.html#overview

Amplifier schematic:

https://safe.nrao.edu/wiki/pub/Main/PafDevelop/Cryo_amp_schematic.pdf

Component layout:

https://safe.nrao.edu/wiki/pub/Main/PafDevelop/pcb_comp_layout.pdf

Problems with LNAs

4/9/13

Anish reports the following dead amps:

2X, 9X, 14X, 6Y, 8Y, 10Y, 14Y

These amps were removed from the dewar. Upon inspection, we found considerable solder paste debris and residual flux. Because of this, all remaining amps were removed, cleaned, and inspected.

The amps use a Teflon based (Cuflon) PC board soldered to at baseplate. Two end plates are bolted onto a base plate. A cover plate then bolts down to the baseplate.

(Note, this is S/N 020 after soldering the top surface of the PC board to the end plates. The top cover is then rounded-over to accommodate the fillet of solder.)

We noticed that the top cover and the baseplate were the same length, and fit very tight. If the baseplate cools quicker than the cover, then the cover can cause excessive stress on the baseplate-to-endplates. The gap formed by this can then stress the coax connectors and pc board.

The solution was to solder the two endplates to the top surface of the Cuflon. Also, we machined about 0.005” off the top cover to insure it was shorter than the baseplate. The solder created a fillet between the endplates and baseplate, so each top cover was machined to accommodate this.

Using a spectrum analyzer and a probe, we determined the 1st transistor was blown in all except 14Y. In amp 14Y, the 2nd transistor was dead. In two amps the plastic case of the transistor broke in two pieces as it was being unsoldered, thus lending credence to the thermal stress theory.

Using spare original BFU725F transistors, all bad transistors were replaced, and the amps then tested at 300K. The amps were next cooled to 15k and checked. All had proper gain except 14Y.

Transistor #2 was replaced in 14Y. Gain dropped to 20db at 15K. Warmed up and its nominal gain returned at room temp. Inspected with microscope and didn’t see any obvious problems. Still concerned about the cover, so re-cooled with cover off. During the cooldown, at ~100K, the gain dropped to ~20db. During the warmup, nominal gain did not return. Probed and found the 1st transistor dead. Replaced and cooled (OK at 15K)

7/9/13

All amps repaired and tested at 15K in test dewar. Reinstalling amps in PAF dewar.

7/11/13

PAF Receiver is cold in test building. Anish, Bill, and Eric are in Green BAnk. We found the following dead channels: 1X, 10X, 12X, 1Y, 3Y, 7Y (note there are no duplicates from the dead ones from 4/9/13.)

Our group brainstormed and now theorize that the amps are dying after 10-15 cooldowns. (There isn’t any firm data on the cooldowns done to date. We don’t have any good ideas why it’s mostly the first transistor. Right now we have 12 original transistors left in stock.)

The theory is that the PC board pad is acting as a shear force in the horizontal direction (along the board dimension) and the feet of the device is 1/3 outside the device and 2/3 within. The Duroid, external pad and solder blob move one way and the plastic encapsulated inner part goes the other way.

Our goal is to get on the GBT, but this is pointless with bad LNA’s. Digikey has BFU725F transistors for $0.34 each, so we purchased 100, and will replace all transistors in all 38 amps. We will replace both transistors in all amps, except those identified on 4/9/13 and already replaced. Until we figure out what’s going on, the few remaining original transistors will be kept in Green BAnk, and not installed in any amp.

7/16/13

Sent a bad transistor to Bill in Cville. He and Tod are going to look at them. Our best guess is that the bond wire between the solder pad and the encapsulated devices is breaking due to thermal stress. This could be internal to the transistor, or possibly the Cuflon substrate is moving and stressing the solder pads on the transistor. A couple of pictures from Tod are shown below: