EE 254Solution for SampleTest 4
Open book, open notes, no computers.
1. Three tri-state bi-directional registers R1, R2, and R3 are connected to a common bus. R1 has load input load 1 and tri-state enable input enable 1. R2 and R3 have tri-state enables and loads respectively. Assume the initial contents of the registers are as follows: R1 = 5, R2 = 6, R3 = 7. The waveform below indicates the signals that are applied to the registers. t1, t2, and t3 are time markers. Complete the table showing the contents of the registers at the indicated time marks.
R1 / R2 / R3t0 / 5 / 6 / 7
t1 / 6 / 6 / 6
t2 / 6 / 6 / 6
t3 / 6 / 6 / 6
2. Design a 3-bit counter using rising edge triggered j-k master-slave flip-flops with the counting sequence ... 1,4,2,7,1,4,2,7,... Use the outputs of the flip-flops as the output of the counter (Moore design). Construct a state table showing the present state and the next state including any don’t cares marked with x’s. Construct the K-maps and minimize the logic needed to produce the counter. Sketch the circuit and check for LOCKOUT. If a lockout problem exists DO NOT FIX IT just list the states that cause the problem.
A / 00 / 01 / 11 / 100 / xx / 1x / xx / 1x
1 / x1 / xx / x1 / xx
B / 00 / 01 / 11 / 10
0 / xx / 0x / xx / x0
1 / 1x / xx / x1 / xx
present next
A / B / C / A / B / C
0 / 0 / 0 / X / X / X
0 / 0 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 1 / 1
0 / 1 / 1 / X / X / X
1 / 0 / 0 / 0 / 1 / 0
1 / 0 / 1 / X / X / X
1 / 1 / 0 / X / X / X
1 / 1 / 1 / 0 / 0 / 1
C / 00 / 01 / 11 / 10
0 / xx / x1 / xx / 1x
1 / 0x / xx / x0 / xx
JA = KA = 1 JB = KB = A JC = KC = ~A
3. The partial Verilog code to the right is used to create an 8-bit
shift register. The shift register has clock s, data in d, and
an 8 bit Q output.
Complete the Verilog code.
4. Given below is a 3 to 8 decoder with active low outputs, three address inputs A, B, C, one active high and two active low enable inputs G1, G2A, and G2B respectively. U1, U2, and U3 are I/O devices with active low chip selects as shown. There are six low order addresses A0, A1, A2, A3, A4, and A5 with A0 being the least significant bit. Place the appropriate address bits (A0, A1, A2, A3, A4, and A5) on the decoder inputs, and connect the appropriate decoder outputs to the I/O devices so that the I/O devices have the following addresses:
U1 @ 20 hex U2 @ 30 hex U3 @ 3C hex
5. Answer the questions below about the Verilog code shown.
A) What is the counting sequence for this counter assuming that it is reset on start up? 0,1,4,10,5,6,0,…
B) Does this counter have lock out? No.
C) What does state 12 = 1100 map into (next state)?
D) You can eliminate at least one line from the case statement without changing the logical function. What is it? 6->0.
//Exam4.v
module Exam4(clk, reset, state);
parameter n = 4;
input clk, reset;
output [n-1:0]state;
reg [n-1:0]state;
//
always @(posedge clk)
if(reset)
state = 0;
else
begin
case (state)
4'b0000:state = 4'b0001; //0 -> 1
4'b0001:state = 4'b0100; //1 -> 4
4'b0010:state = 4'b0001; //2 -> 1
4'b0100:state = 4'b1010; //4 -> 10
4'b1001:state = 4'b1010; //9 -> 10
4'b1010:state = 4'b0101; //10-> 5
4'b0101:state = 4'b0110; //5 -> 6
4'b0110:state = 4'b0000; //6 -> 0
4'b1000:state = 4'b0001; //8 -> 1
default:state = 4'b0000;
endcase
end
endmodule
6. Given a memory system, which has 128K of 16-bit words. Answer the following:
A) How many address lines does it take to address any word in memory?
2n = 128,000 n = 17 (rounded).
B) If the memory is constructed of 64K X 8 chips how many chips are used?
2 * 8 = 16 and 64k * 2 = 128k therefore 2 * 2 = 4 chips are needed.
7. Given the Verilog module to the right with thesignals inputted to the module as shown below:
Complete the waveform for Q as indicated
below.
Q is initially 0.