10/10

ECE 20B, Winter 2004

Midterm 2Thursday 02/26/04

Version-1

Last Name: ______

First Name:______

Student ID #:______

One page of notes, closed book, no calculators.

For any problem be sure to show as much work as you can for partial credit.

Write your solution in PEN. You may work using a pencil however you will only be graded for work done in PEN.

Circle your answers!

1 (8 pts)
2 (8 pts)
3 (6 pts)
4 (6 pts)
5 (10 pts)
6 (15 pts)
7 (18 pts)
Total (71 pts)

There are 7 problems on 10 pages (including this page)

Lab Problems are 1 & 2


Question #1 (8 pts)

(a)  (6 pts) For the circuit shown below, complete the timing diagram. Assume that the RC time in Figure 1 is short compared to the square wave period. You may assume that the initial voltage at point A is 0.7V.

(b)  (2 pts) What type of basic gate does the circuit represent with respect to the output at point B?

Question #2 (8 pts)

(a)  (6 pts) For the circuit shown below, complete the timing diagram.

(b)  (2 pts) Why do we need two flip-flops in the enter key detector circuit?

Question #3 (6 pts)

(a) (3 pts) Give the characteristic table of a JK flip-flop.

(b) (3 pts) Complete the timing diagram below for a rising edge

triggered J/K flip flop. Initially Q=0,Q’=1.

Question #4 (6 pts)

Assume you are given a 1024 x 4 memory chip.

(a) (2 pts) How many address lines does the chip have?

(b) (2 pts) How many data input lines does it have?

(c) (2 pts) If you are given two 1024 x 4 memory chips with enable lines show

how you would wire them up to create a 2048 x 4 memory chip. (Any additional logic

necessary can be used.)


Question #5 (10 pts)

Two SR flip-flops are connected as shown below. Draw waveforms for Y and Q. The waveforms for J, K and C are provided. Initially Y=0 and Q=1. (Both flip-flops are triggered by a rising edge.)


Question #6 (15 pts)

Consider the circuit diagram below.

(a)  (10 pts) Fill in the state table below. Be careful not to mix up F0,F1 and F2!

Present State / Xi / Next State / Yi
QF0(t) / QF1(t) / QF2(t) / QF0(t+1) / QF1(t+1) / QF2(t+1)

(b) (5 pts) Can you describe what this circuit does? (Hint: what is the output at cycle 2i for any positive integer i ?)

Question #7 (18 pts)

You are required to design a sequence recognizer. The sequence recognizer has a single input X and a single output Z. Every time the last four bits of the sequence input are 0011 (0 then 0 then 1 then 1), the output Z=1 otherwise the output is Z=0. Implement this as a Mealy machine (Four States).

Follow the instructions below:

1)  You must use A,B,C,D as the four states of the sequence recognizer.

2)  You need two bits S1,S0 to encode the states. Use A=00,B=01,C=10,D=11.

3)  You must use a JK flip-flop for S1 and a D flip-flop for S0.

Please show:

(a) (5 pts) A state diagram for the sequence recognizer.

(b) (5 pts) A state table for the state diagram.

(c) (4 pts) K-maps for finding the inputs to the flip-flops and output.

(d) (4 pts) Final schematic representation of the sequence recognizer.