The
8051
Instruction
Set
Revised 11/30/08
Jerry H. Tucker
MEMORY
CODE MEMORY Internal ROM selected by = 1
CM = CM(0..0FFFFH) = CM(0..0FFFFH;7..0)[1]
ON CHIP DATA MEMORY
DM = DM(0..FFH) = DM(0..FFH;7..0)
Note: Direct addressing of DM(80..FFH) accesses special function registers (SFR). Indirect addressing (i.e. @R0, @R1) must be used to accesses DM(80..FFH).
ON CHIP BIT ADDRESSIABLE MEMORY
BADM = DM(20..2F) = BADM(0..0FF) = BADM(0..0FF;0) ;Bit addressable data memory.
EXTERNAL RAM MEMORY
XM = XM(0..0FFFFH) = XM(0..0FFFFH;7..0)
INTERNAL REGISTERS AND PORTS
PC = PC(15..0)
SP = SP(7..0)
DPTR = DPTR(15..0)
PSW = CY|AC|F0|RS1|RS0|OV|-|P[2]
TCON = TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0
BADM(87H..80H) = P0 = P0(7..0) = BADM(87H..80H)
BADM(8FH..88H) = TCON =BADM(8FH..88H)
BADM(97H..90H) = P1 = P1(7..0) =BADM(97H..90H)
BADM(9FH..98H) = SCON =BADM(9FH..98H)
BADM(A7H..A0H) = P2 = P2(7..0) =BADM(A7H..A0H)
BADM(AFH..A8H) = IE =BADM(AFH..A8H)
BADM(B7H..B0H) = P3 = P3(7..0) =BADM(B7H..B0H)
BADM(BFH..B8H) = IP =BADM(BFH..B8H)
BADM(C7H..C0H) = BADM(C7H..C0H)
BADM(CFH..C8H) = BADM(CFH..C8H)
BADM(D7H..D0H) = PSW =BADM(D7H..D0H)
BADM(DFH..D8H) = BADM(DFH..D8H)
BADM(E7H..E0H) = ACC = A = A(7..0) = BADM(E7H..E0H)
BADM(EFH..E8H) = BADM(EFH..E8H)
BADM(F7H..F0H) = B =BADM(F7H..F0H)
BADM(FFH..F8H) = BADM(FFH..F8H)
RESET
PC 0, A 0, B 0, PSW 0, SP 7H, SPTR 0, P0-P3 0FFH,
IP XXX00000B, IE 0XX00000B, TMOD 0, TCON 0, TH0 0, TL0 0, TH1 0, TL1 0, SCON 0, PCON 0XXXXXXXB, DPTR 0000H
INTERNAL DATA MEMORY
00H-07H / RB0 / Register Bank 008H-0FH / RB1 / Register Bank 1
10H-17H / RB2 / Register Bank 2
18H-1FH / RB3 / Register Bank 3
20H-27H / BAM(00H)-BAM(3FH) / Bit addressable memory
28H-2FH / BAM(40H)-BAM(7FH) / Bit addressable memory
30H-37H / Available to user.
38H-3FH / Available to user.
40H-47H / Available to user.
48H-4FH / Available to user.
50H-57H / Available to user.
58H-5FH / Available to user.
60H-67H / Available to user.
68H-6FH / Available to user.
70H-77H / Available to user.
78H-7FH / Available to user.
80H / P0 / SFR
81H / SP
82H / DPL / DPTR
83H / DPH
84H
85H
86H
87H / PCON
88H
89H / TMOD / Timer/Counter Mode Control
8AH / TL0
8BH / TL1
8CH / TH0
8DH / TH1
98H / SCON / Serial Port control
99H / SBUF
Special Function Memory (Bit addressable)
BAM / P0.7 / P0.6 / P0.5 / P0.4 / P0.3 / P0.2 / P0.1 / P0.080H / 87 / 86 / 85 / 84 / 83 / 82 / 81 / 80 / P0
TF1 / TR1 / TF0 / TR0 / IE1 / IT1 / IE0 / IT0
88H / 8F / 8E / 8D / 8C / 8B / 8A / 89 / 88 / TCON
P1.7 / P1.6 / P1.5 / P1.4 / P1.3 / P1.2 / P1.1 / P1.0
90H / 97 / 96 / 95 / 94 / 93 / 92 / 91 / 90 / P1
SM0 / SM1 / SM2 / REN / TB8 / RB8 / TI / RI
98H / 9F / 9E / 9D / 9C / 9B / 9A / 99 / 98 / SCON
P2.7 / P2.6 / P2.5 / P2.4 / P2.3 / P2.2 / P2.1 / P2.0
A0H / A7 / A6 / A5 / A4 / A3 / A2 / A1 / A0 / P2
EA / ES / ET1 / EX1 / ET0 / EX0
A8H / AF / AE / AD / AC / AB / AA / A9 / A8 / IE
/ / T1 / T0 / / / TXD / RXD
P3.7 / P3.6 / P3.5 / P3.4 / P3.3 / P3.2 / P3.1 / P3.0
B0H / B7 / B6 / B5 / B4 / B3 / B2 / B1 / B0 / P3
PS / PT1 / PX1 / PT0 / PX0
B8H / BF / BE / BD / BC / BB / BA / B9 / B8 / IP
C0H / C7 / C6 / C5 / C4 / C3 / C2 / C1 / C0 / -
C8H / CF / CE / CD / CC / CB / CA / C9 / C8 / -
CY / AC / FO / RS1 / RS0 / OV / P
D0H / D7 / D6 / D5 / D4 / D3 / D2 / D1 / D0 / PSW
D8H / DF / DE / DD / DC / DB / DA / D9 / D8 / -
E0H / E7 / E6 / E5 / E4 / E3 / E2 / E1 / E0 / ACC
E8H / EF / EE / ED / EC / EB / EA / E9 / E8 / -
F0H / F7 / F6 / F5 / F4 / F3 / F2 / F1 / F0 / B
F8H / FF / FE / FD / FC / FB / FA / F9 / F8 / -
NOTATION DEFINITIONS
n {0,1}, i {0,...,7}, bit {0,1}, byte {0,...,255}, dbyte {0,...,255}
short {0,...,03FFH}, addr {0,...,0FFFFH}
Rn {R0, R1}, Ri {R0, R1, ..., R7}
Ri = DM(i+8*RBANK)
RBANK = RS1*2+RS0
ARITHMETIC INSTRUCTIONS
ADD / A,#byte / ;A A + byteADD / A,@Rn / ;A A + DM(Rn)
ADD / A,Ri / ;A A + Ri
ADD / A,byte / ;A A + DM(byte)
ADDC / A,#byte / ;A A + byte + CY
ADDC / A,@Rn / ;A A + DM(Rn) + CY
ADDC / A,Ri / ;A A + Ri + CY
ADDC / A,byte / ;A A + DM(byte) + CY
SUBB / A,#byte / ;A A - byte - CY
SUBB / A,@Rn / ;A A - DM(Rn) - CY
SUBB / A,Ri / ;A A - Ri - CY
SUBB / A,byte / ;A A - DM(byte) - CY
INC / A / ;A A + 1
INC / @Rn / ;DM(Rn) DM(Rn) + 1
INC / Ri / ;Ri Ri + 1
INC / byte / ;DM(byte) DM(byte) + 1
INC / DPTR / ;DPTR DPTR + 1
DEC / A / ;A A - 1
DEC / @Rn / ;DM(Rn) DM(Rn) - 1
DEC / Ri / ;Ri Ri - 1
DEC / byte / ;DM(byte) DM(byte) - 1
MUL / AB / ;B|A A*B
DIV / AB / ;A A/B, B A MOD B
DA / A / ;IF AC=1 OR A(3..0) > 9 THEN A A+6
;IF CY=1 OR A(7..4) > 9 THEN AA+60H
Rn {R0, R1}, Ri {R0, R1, ..., R7}
LOGICAL INSTRUCTIONS
ANL / A,#byte / ;A A byteANL / A,@Rn / ;A A DM(Rn)
ANL / A,Ri / ;A A Ri
ANL / A,byte / ;A A DM(byte)
ANL / dbyte,#byte / ;DM(dbyte) DM(dbyte) byte
ANL / byte,A / ;DM(byte) A DM(byte)
ORL / A,#byte / ;A A byte
ORL / A,@Rn / ;A A DM(Rn)
ORL / A,Ri / ;A A Ri
ORL / A,byte / ;A A DM(byte)
ORL / dbyte,#byte / ;DM(dbyte) DM(dbyte) byte
ORL / byte,A / ;DM(byte) A DM(byte)
XRL / A,#byte / ;A A byte
XRL / A,@Rn / ;A A DM(Rn)
XRL / A,Ri / ;A A Ri
XRL / A,byte / ;A A DM(byte)
XRL / dbyte,#byte / ;DM(dbyte) DM(dbyte) byte
XRL / byte,A / ;DM(byte) A DM(byte)
CLR / A / ;A 0
CPL / A / ;A
RL / A / ;A A(6..0)|A(7)
RLC / A / ;CY|A A|CY
RR / A / ;A A(0)|A(7..1)
RRC / A / ;A|CY CY|A
SWAP / A / ;A A(3..0)|A(7..4)
Rn {R0, R1}, Ri {R0, R1, ..., R7}
DATA MOVE INSTRUCTIONS
MOV / A,#byte / ;A byteMOV / A,@Rn / ;A DM(Rn)
MOV / A,Ri / ;A Ri
MOV / A,byte / ;A DM(byte)
MOV / @Rn,A / ;DM(Rn) A
MOV / @Rn,#byte / ;DM(Rn) byte
MOV / @Rn,byte / ;DM(Rn) DM(byte)
MOV / Ri,A / ;Ri A
MOV / Ri,#byte / ;Ri byte
MOV / Ri,byte / ;Ri DM(byte)
MOV / byte,A / ;DM(byte) A
MOV / dbyte,#byte / ;DM(dbyte) byte
MOV / byte,@Rn / ;DM(byte) DM(Rn)
MOV / byte,Ri / ;DM(byte) Ri
MOV / dbyte,byte / ;DM(dbyte) DM(byte)
MOV / DPTR,#addr / ;DPTR addr
MOVC / A,@A + DPTR / ;A CM(A+DPTR)
MOVC / A,@A + PC / ;A CM(A+PC)
MOVX / A,@DPTR / ;A XM(DPTR)
MOVX / A,@Rn / ;A XM(P2|Rn)
MOVX / @DPTR,A / ;XM(DPTR) A
MOVX / @Rn,A / ;XM(P2|Rn) A
PUSH / byte / ;DM(SP+1) DM(byte), SP SP + 1
POP / byte / ;DM(byte) DM(SP), SP SP - 1
XCH / A,Ri / ;A Ri
XCH / A,byte / ;A DM(byte)
XCH / A,@Rn / ;A DM(Ri)
XCHD / A,@Rn / ;A(3..0) DM(Rn;3..0)
Rn {R0, R1}, Ri {R0, R1, ..., R7}
PROGRAM AND MACHINE CONTROL
CALL / Note: Assembler translates CALL to ACALL or LCALLACALL / short / ;DM(SP+2)|DM(SP+1) PC+2,
;PC(10..0) short, SP SP + 2
LCALL / addr / ;DM(SP+2)|DM(SP+1) PC+3,
;PC(15..0) addr, SP SP + 2
RET / ;PC DM(SP)|DM(SP-1), SP SP-2
RETI / ;PC DM(SP)|DM(SP-1), SP SP-2
;Reenable equal or lower priority INT
JMP / Note: JMP is translated to AJMP, LJMP, or SJMP.
AJMP / short / ;PC(10..0) short
LJMP / addr / ;PC(15..0) addr
SJMP / byte / ;PC PC + 2 + byte(7)..byte(7)|byte
JMP / @A+DPTR / ;PC DPTR + A
JZ / byte / ;IF A = 0 THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;ELSE PC PC+2
JNZ / byte / ;IF A 0 THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;ELSE PC PC+2
CJNE / A,dbyte,byte / ;IF A DM(dbyte) THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;IF A < DM(dbyte) THEN CY 1
;ELSE CY 0
CJNE / A,#dbyte,byte / ;IF A dbyte THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;IF A < dbyte THEN CY 1
;ELSE CY 0
CJNE / Rn,#dbyte,byte / ;IF Rn dbyte THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;IF A < DM(dbyte) THEN CY 1
;ELSE CY 0
CJNE / @Rn,#dbyte,byte / ;IF DM(Rn) dbyte THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;IF A < dbyte THEN CY 1
;ELSE CY 0
DJNZ / Rn,byte / ;Rn Rn-1, IF (Rn-1) 0 THEN
;PC PC + 2 + byte(7)..byte(7)|byte
;ELSE PC PC + 2
DJNZ / dbyte,byte / ;DM(dbyte) DM(dbyte)-1,
;IF (DM(dbyte)-1) 0 THEN
;PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC + 3
NOP / ;PC PC + 1
BIT MANIPULATION INSTRUCTIONS
CLR / C / ;CY 0CLR / byte / ;BADM(byte) 0
SETB / C / ;CY 1
SETB / byte / ;BADM(byte) 1
CPL / C / ;CY
CPL / byte / ;BADM(byte)
ANL / C,byte / ;CY CY BADM(byte)
ANL / C,/byte / ;CY CY
ANL / byte,bit / ;BADM(byte) BADM(byte) bit
ORL / C,byte / ;CY CY BADM(byte)
ORL / C,/byte / ;CY CY
ORL / byte,bit / ;BADM(byte) BADM(byte) bit
MOV / C,byte / ;CY BADM(byte)
MOV / byte,C / ;BADM(byte) CY
BIT JUMP INSTRUCTIONS
JB / dbyte,byte / ;IF BADM(dbyte) = 1 THEN;PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC+3
JNB / dbyte,byte / ;IF BADM(dbyte) = 0 THEN
;PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC+3
JBC / dbyte,byte / ;IF BADM(dbyte) = 1 THEN
; BADM(dbyte) 0
; PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC+3
JC / byte / ;IF CY = 1 THEN
;PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC+3
JNC / byte / ;IF CY = 0 THEN
;PC PC + 3 + byte(7)..byte(7)|byte
;ELSE PC PC+3
INSTRUCTIONS THAT AFFECT FLAGS (incomplete)
Instruction / CY OV AC / Instruction / CY OV ACADD / X X X / CLR C / 0 - -
ADDC / X X X / CPL C / X -
ANL C,bit / X - -
SUBB / X X X / ANL/ C,bit / X - -
MUL / X X - / ORL C,bit / X - -
DIV / 0 X - / ORL/ C,bit / X - -
DA / X - - / MOV C,bit / X - -
XRL / - - - / CJNE / X - -
CPL A / - - -
SETB C / 1 - - / DEC / - - -
SWAP A / - - - / DJNZ / - - -
RR, RL / - - - / INC / - - -
RRC, RLC / X - -
Note: The flags can also be effected by operations on the PSW or bits in the PSW.
The zero flag Z is set iff ACC = 0, the parity flag P is set iff ACC contains an odd number of 1’s.
EX 8051 ASSEMBLEY LANGUAGE EXAMPLES PAGE 1
1 $MOD51
2 $TITLE(8051 ASSEMBLEY LANGUAGE EXAMPLES)
3 $PAGELENGTH(55) ;SET FOR YOUR PRINTER
4 $PAGEWIDTH(132)
5 $SYMBOLS ;INCLUDE SYMBOLS IN LISTING
6 ;*******************************************************
7 ;
8 ; FUNCTION: EX - 8051 ASSEMBLY LANGUAGE EXAMPLES
9 ;
10 ;******************************************************
11 ;
0038 DSEG AT 38H ;DATA SEGMENT
0038 13 STACK: DS 8 ;RESERVE 8 BYTES FOR STACK
---- 14 CSEG ;CODE SEGEMNT
0000 15 ORG 0
0000 16 RESET:
0000 020030 17 JMP START ;SKIP RESERVED MENORY
0003 18 ORG 3H
0003 19 INTR0: ;LCALL ISR
0003 32 20 RETI
000B 21 ORG 0BH
000B 22 TIME0:
000B 32 23 RETI
0013 24 ORG 13H ;ENTRY POINT FOR INTR1
0013 25 INTR1:
0013 32 26 RETI
001B 27 ORG 1BH
001B 28 TIME1:
001B 32 29 RETI
0023 30 ORG 23H
0023 31 COM:
0023 32 32 RETI
002B 33 ORG 2BH
002B 34 TIME2:
002B 32 35 RETI
EX 8051 ASSEMBLEY LANGUAGE EXAMPLES PAGE 2
37 ;START OF PROGRAM
0030 38 ORG 30H
0030 758137 39 START: MOV SP,#STACK - 1 ;INITIALIZE STACK POINTER
---- 40 DSEG ;SWITCH TO DATA
0040 41 X: DS 1 ;RESERVE BYTE FOR X
0041 42 Y: DS 1 ;RESERVE BYTE FOR Y
0042 43 Z: DS 1 ;RESERVE BYTE FOR Z
---- 44 CSEG ;SWITCH BACK TO CODE
45 ;DATA MOVE INSTRUCTIONS
0033 74FF 46 MOV A,#-1 ;LOAD A WITH 0FFH
0035 E7 47 MOV A,@R1 ;LOAD A WITH DATA MEM POINTED TO BY R1
0036 E9 48 MOV A,R1 ;LOAD A WITH CONTENTS OF R1
0037 E560 49 MOV A,2*30H ;LOAD A WITH CONTENTS OF DATA MEM 60H
0039 E5A0 50 MOV A,P2 ;LOAD A WITH CONTENTS OF PORT 2
003B F6 51 MOV @R0,A ;STORE A IN DATA MEM POINTED TO BY R0
003C 77FF 52 MOV @R1,#0FFH ;PUT ALL 1'S IN LOC POINTED TO BY R1
003E A67F 53 MOV @R0,7FH ;READ DATA MEMORY 7FH AND STORE IN
54 ;DATA MEMORY POINTED TO BY R0.
0040 FF 55 MOV R7,A ;STORE A IN REGISTER R7
0041 7E55 56 MOV R6,#01010101B ;PUT 55H IN R6
0043 7850 57 MOV R0,#50H ;LOAD R0 WITH 50H = 80
0045 7F51 58 MOV R7,#01010001B ;LOAD R7 WITH 51H = 81
0047 AD37 59 MOV R5,55 ;PUT CONTENTS OF LOCATION 55 IN R5
0049 F537 60 MOV 55,A ;PUT A IN DATA MEM LOC 55
004B 7537AA 61 MOV 55,#0AAH ;PUT AAH IN DM LOC 55 DECIMAL
004E 85FF90 62 MOV P1,#0FFH ;SET P1 TO ALL 1'S
0051 87A0 63 MOV P2,@R1 ;SET P2 TO DATA MEM POINTED TO BY R1
0053 85B080 64 MOV P0,P3 ;READ PORT 3 AND OUTPUT IT TO P0
0056 858000 65 MOV 0,P0 ;READ PORT 0 AND SAVE IN DATA MEM 0
0059 AAA0 66 MOV R2,P2 ;READ P2 AND SAVE IT IN R2
005B 90006F 67 MOV DPTR,#A_TABLE ;POINT DPTR TO LOOK UP TABLE
005E 740A 68 MOV A,#0AH ;PUT HEX B = 1011 = 11 IN ACC
0060 93 69 MOVC A,@A+DPTR ;CONVERT IT TO ASCII (A = 'B')
0061 E4 70 CLR A ;LOAD A WITH 0
0062 83 71 MOVC A,@A+PC ;PUT OPCODE OF PC+0 (NEXT INST) IN A
0063 D3 72 SETB C ;SET CARRY BIT
0064 103E06 73 JBC 39.6,EXIT ;IF BIT 39.E = 27H.6 = 0B3H IS SET
0067 103E03 74 JBC 27H.6,EXIT ;CLEAR AND JUMP TO EXIT
006A 10BE00 75 JBC 0BEH,EXIT ;ALL THREE ARE THE SAME
006D 80C1 76 EXIT: JMP START ;LOOP FOREVER
006F 77 A_TABLE:
006F 30 78 DB '0' ;PUT ASCII VALUE OF 0 IN CODE MEMORY
0070 31 79 DB '1' ;ASCII 1
0071 32 80 DB '2' ;ASCII 2
0072 33 81 DB '3' ;ASCII 3
0073 34 82 DB '4' ;ASCII 4
0074 35 83 DB '5' ;ASCII 5
0075 36 84 DB '6' ;ASCII 6
0076 37 85 DB '7' ;ASCII 7
0077 38 86 DB '8' ;ASCII 8
0078 39 87 DB '9' ;ASCII 9
0079 41 88 DB 'A' ;ASCII A
007A 42 89 DB 'B' ;ASCII B
007B 43 90 DB 'C' ;ASCII C
007C 44 91 DB 'D' ;ASCII D
007D 45 92 DB 'E' ;ASCII E
007E 46 93 DB 'F' ;ASCII F
94 END
1
12/27/2018 -
[1] The code memory address space consists of 216 words. Each word contains 8 bits.
[2] Set if accumulator has odd parity.