1005DotOrg_Sidebar.doc
Keywords: debug, test, design-for-debug
@head:New Industry Consortium Targets Silicon Debug
@text:Semiconductor-design, manufacturing-test, and silicon-debug companies are rallying under the auspices of the newly formed Design-for-Debug (DFD) Consortium. Their mission is to define and promote the products, methodologies, and industry standards that are required to make functional debug more efficient in chips mounted in silicon prototypes or systems (referred to as “in situ”).
The first order of business for the DFD Consortium is to raise awareness and create a forum in which tool interoperability and methodology issues can be identified and investigated. Efforts will be targeted at providing both DFD users and solution providers with a better understanding of product-interoperability requirements and practical design guidelines. Charter members include: Corelis Inc.; DAFCA Inc.; First Silicon Solutions Inc. (FS2); Intellitech Corp.; JTAG Technologies; Fidel Muradali (consultant), and Novas Software Inc.
The process for productizing and delivering chips to market is typically broken into two major stages: concept-to-prototype and prototype-to-volume. Recent trends indicate that while the amount of time is stable to slightly decreasing for the first stage, the time required to move from prototype to volume production is increasing. The debug of first-silicon prototypes has become a major bottleneck that requires collaboration between the design and test disciplines.
Because this problem is getting worse, now is the time for this effort. Deep-submicron effects on signal integrity and semiconductor-manufacturing process variations as well as functional errors and performance shortcomings have become endemic. Access to internal signals and visibility into the silicon device itself during the testing of chips in situ is tremendously limited. The process of isolating and analyzing silicon problems has therefore grown extremely tedious and time consuming. This limitation makes it increasingly more difficult to determine whether silicon errors are undetected functional-design bugs or physical-manufacturing defects.The time neededto track down problems once a chip is in its prototype system has therefore become unpredictable and costly--mainly because a broad set of silicon-debug and diagnosis solutions is not yet commercially available.
“In-Situ” Prototype Validation
Whereas manufacturing tests rely on widely adopted design-for-test (DFT) methodologies, system validation has no equivalently adopted methodology. The steps to achieve system validation are understood: run system-level applications while the device is in situ to ensure that it operates according to specification. When unexpected silicon behavior arises, however, many engineering teams must resort to reproducing scenarios using emulation or software simulation. After all, directly observing internal silicon signals is impossible. Only after reproducing a bug in these environments can engineers proceed to trace its origin. This entire process is time consuming and difficult.
To speed up the debug portion of system validation, engineers need visibility into the internal silicon behavior. Yet detailed examination of actual silicon behavior is only possible if sufficient “on-chip” hardware has been implemented. Such hardware must be dedicated to aiding the silicon debug of the device (DFD logic). Currently, very few designs contain some type of DFD logic. No standard or general guidelines exist for DFD implementation and usage.
As a result, significant resources are required to gain the smallest insight into the silicon. Indeed, a multitude of tools and steps are utilized today to narrow the scope of silicon diagnosis efforts before results can be manually mapped back to the design. There are silicon-debug tools available that target specific aspects of the system. They include software-development debug tools that provide address and register-based data as well as tools that are oriented to finding physical defects. While these tools have made progress in alleviating some issues, the lack of a complete silicon-debug-to-analysis flow has resulted in disparate, proprietary solutions.
The DFD approach requires:
1. The implementation of on-chip logic to enhance the ability to retrieve crucial data through improved design observability
2. Associated software and hardware to transport signal data off chip
3. The extrapolation of the limited retrievable data using process-automation and analysis techniques for system-level silicon validation
DFD solutions must span design implementation and hardware validation. The design team implements and verifies the DFD logic while the hardware team utilizes the DFD functionality. In most cases, the hardware team feeds back the silicon data acquired through the DFD logic to the design team for analysis and assistance with silicon debug.
To ensure success, DFD solutions must be created and reviewed by experts across a range of disciplines. The DFD Consortium consists of charter members with collective experience that brings together the following: design and debug infrastructure, intra-chip connection testing, hardware devices connecting to standardized logical interfaces, test application software, and design comprehension and behavior analysis. The DFD Consortium will thoroughly scope the problems associated with silicon debug and identify the points of convergence for improving the process. To do so, it will use interfaces that bridge logic implementation with signal-data transport through to signal processing and analysis.
Input from end users is critical. Their feedback will influence the development of key components in the silicon-debug value chain. Examples include the on-chip DFD logic infrastructure, methods for getting data off the chip, and techniques for accessing signal data at the board level. Among other examples are the transfer of information to engineering workstations and the software environments required for more efficient silicon analysis and debug. Primary considerations also include the need for standards in order to promote the creation of tools and applications.
The commercial development of well-defined DFD methodologies and interoperable tool flows has the potential to significantly improve the efficiency of silicon debug while lowering development costs and accelerating time-to-volume production for integrated-device manufacturers. The DFD Consortium believes collaboration across the supply chain will accelerate the pace at which silicon-debug solutions can be brought to market--especially as silicon becomes more complicated. For more information or to become a member of the DFD Consortium, visit