Mentor Graphics Tutorial: from VHDL to Silicon layout
Aleksandar Milenkovic
Electrical and Computer Engineering
The University of Alabama in Huntsville
Sparkman dr. 301, AL 35899
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Introduction
This tutorial describes a complete ASIC design flow from VHDL to silicon layout using software from Mentor Graphics Corp. In this tutorial we will design an 8-bit adder described in Figure 1. We assume that the model has already been verified using ModelSim (see
library IEEE;use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADDER is
generic (N : in integer := 8);
port (
A, B : in std_logic_vector(N-1 downto 0);
CI : in std_logic;
S : out std_logic_vector(N-1 downto 0);
COUT : out std_logic);
end ADDER;
architecture RTL of ADDER is
signal RESULT : std_logic_vector(A'length downto 0);
begin
RESULT <= ('0' & A) + ('0' & B) + CI;
S <= RESULT(A'length-1 downto 0);
COUT <= RESULT(A'length);
end RTL;
Figure 1. VHDL code for an 8-bit adder.
The first step is to synthesize the VHDL design into RTL level using Leonardo Spectrum synthesizer.
For your own design, change the directory names and file names of this exercise accordingly. The names and directories do not carry any significance in the design flow, only just for some naming conventions and convenience.
Synthesizing VHDL using Leonardo Spectrum
Step 1. Create directories and invoke leonardo
Create a directory (e.g. $HOME/myadder) and copy file adder.vhd with the source code shown above.
$ mkdir myadder
$ cd myadder
$ mkdir netlsit // directory where edif netlist will be saved
Set working directory.
$ swd
Start leonardo.
$ leonardo &
A pop-up window appears with LeonardoSpectrum3 selected. Hit Ok button and the following window appears (Figure 2).
Figure 2. Leonardo Spectrum.
Step 2. Load the technology library
In the "Technology" tab, expand "ASIC", "ADK", and choose "AMI 0.5 micron (typ)" process. Then click "Load Library".
Step 3. Set some ADK-specific variables
Click on the command window on the bottom right of the screen. Enter the following set of commands:
set vhdl_write_component_package FALSE
set vhdl_write_use_packages {library ieee,adk; use ieee.std_logic_1164.all; use adk.all}
set edifout_power_ground_style_is_net TRUE
set force_user_load_values
set max_fanout_load 14
Note: These commands can be saved in a file, for example setc.tcl. To run the script file click on File -> Run Script pull down menu and then select the script file or enter the following command in the command window:
source setc.tcl
Step 4. Read the VHDL file(s)
Now click on the "Input" tab. Open the file adder.vhd. Click on "Read". Ensure, resource sharing, run elaborate and run pre-optimization are ticked. Now if you choose Tools, then View RTL Schematic, you can see the RTL level synthesis results. See if the schematic matches the VHDL description. Close the schematic window before you proceed to the next step.
Step 5. Optimize design
Click on the "Optimize" tab, make sure "Add I/O Pads" is NOT selected. Now click on "Optimize".
Now if you choose Tools, then View Gate Level Schematic, you can see the technology dependent gate level synthesis results. See if the schematic matches the VHDL description. Close the schematic window before you proceed to the next step.
Step 6. Generate reports for area and delay
Click on "Report" tab, and then click on the "Report Area" button. Save area report in a file (e.g., area-report.txt). Now if you click on the "Report Delay" tab on the bottom left of the screen, and then click on "Report Delay" tab, you can get an estimate of the delay through various critical paths. You can also see the critical path(s) in the schematic if you select “Bring Up Schematic Viewer”.
Step 7. Save the design
Now click on the "Output" tab. Choose the output format to "EDIF" first, and then save the output EDIF file (adder.edf) in the netlist directory. The adder.xdb file is a proprietary database file for loading back into Leonardo Spectrum the same design data. It is not needed elsewhere.
You have now created an industry standard netlist file for use in other EDA programs.
Creating Mentor Graphics schematics from EDIF netlist file and checking new schematics
Step 1. Enter the directory with the netlist
Descend into the netlist directory, where you will find the edif file and the xdb file:
$ cd netlist
Set the netlist as the working directory:
$ swd
Step 2. Create EDDM database and schematic
Run the following script in order to translate the EDIF file into various viewpoints necessary for design with Mentor Graphics:
$ edif2eddm adder.edf
There should be no error messages printed on the screen. This script creates a directory work and in this directory ADDER_8 component. In addition to this, it invokes adk_dve script and creates all necessary veiwpoints: layout, sdl, accusim, ami05, lvs.
Step 3. Examine synthesize schematic using the Design Architect
If you want to examine the synthesized schematic invoke the Design Architect:
$ adk_da &
In the Design Architect window, from the session_palete, select OPEN SHEET and navigate down to work/ADDER_8/RTL/sheet1. What you see is a schematic consisting of components of the standard gate library (Figure 3).
Figure 3. Design Architect.
Quit adk_da.
Creating the IC layout from the schematics
Step 1. Invoke IC station
You should be in the design directory ($HOME/myadder/netlist), and it should also be your working directory.
Invoke IC Station:
$ adk_ic &
Step 2. Create an IC cell
Now create a new cell layout, click "Create". The following screen “Create Cell” appears.
Specify the cell name (adder for example), Attach Library is $ADK/technology/ic/ami05.
Process is $ADK/technology/ic/ami05. Rules File is $ADK/technology/ic/ami05.rules.
Choose Connectivity? With connectivity.
The EDDM Schematic Viewpoint MUST be the layout viewpoint under your design (ie. $MGC_WD/work/ADDER_8/layout).
Click "Logic Loading Options" and choose Flat on "Logic Loading".
Accept the default options, and click OK to close all the forms.
Figure 4. Create cell.
Step 3. Autofloorplan the IC cell
This step sets out the guidelines for placing ports and logic for the new cell.
From IC Pallets go to the Floorplan and choose Autofp (autofloorplan). Allow all options to default simply by clicking on OK in response to the Autofloorplan Options form. Use View -> All from the top menu bar to see the automatically generated floor plan. You will see a series of boxes enclosed by solid green bars along each edge. The boxes indicate the rows into which cells will be organized. The solid bars indicate edges of the cells along which physical ports will be placed.
Step 4. Placing the standard cells
In the Place & Route palette go to Autoplc section and choose StdCel. Accept the default options in the dialog box. You should see individual cells placed in the floorplan boxes. Cell locations are determined by their interconnectivity. Cells which share connections are placed near one another. You may wish to experiment with the results obtained thus far by selecting different Autofloorplan and Autoplace options.
Step 5. Placing ports
From the Autoplc section of the Place & Route palette select Ports. You can allow the options to default for now, but you may wish to experiment with them later. You will see lightly shaded areas along the port bars at the edge of the layout.
At this point, it is assumed that you have arrived at a satisfactory initial placement for all cells of the layout. Prior to autorouting the interconnect, you may wish to observe a "rats nest" view of the signals connecting the various cells. This is sometimes useful to engineers for determining sources of routing congestion. To observe a rats nest of signal connections, select Connectivity -> Net -> Restructure -> All signal. It may look a little messy, but keep in mind that it doesn't change the layout whatsoever.
Step 6. Route the IC cell
From the Place & Route palette select "All" from the "Autorou" subsection. A submenu will appear in the editing window. Select "Options" and "Expert" options and select "Channel Over Cell Routing". From the "OCR" options menu set the step size to 0.5 and the "Operation Mode Type" to "Center Weighted". Click OK on all the forms and begin autorouting. Depending on the size of the design this may take several minutes. When the process has completed the mouse pointer changes from an hourglass back to an arrow and the results of the process are in a text transcript found in the current directory.
Step 7. Find and route overflows
This step is necessary even if overflows don’t immediately appear in the routed layout. Several small overflows may still exist, which can be expected for larger designs. When zoomed out small overflows may not be viewable, but may still exist. To select all overflows in the design, enter command "check over". In the form window that appears select "All" and OK the form. Next, from the Place and Route palette menu select "Overflw". If the response "An object of type Overflow must be selected" appears in the status block, there are no overflows to route. Otherwise, the overflows should be routed, manually or automatically.
Save the cell layout: Save the layout by File -> Cell -> Save Cell -> Current Context. You may save the layout and exit the ICgraph session at any time. To re-load the layout later, choose open from the IC staton palette. If you wish to make changes to the cell after you save, you must select File -> Cell -> Reserve Cell -> Current Context.
Step 8. Compacting
The autorouter’s objective is to complete as many connections in the design as possible with less regard for wasted area. A layout compactor is available allowing you to “squashe” things together where there is a little bit of unused space. To run compactor, go to PR Edit section of the Place & Route palette and select Compct. We want to compact in both the horizontal and vertical dimensions, so do this twice: once selecting down direction, and then again selecting left direction. Do not do this more than once along a given axis – it rarely gives any improvement, and can lead to layout errors.
Step 9. Save the IC cell
Save the layout. This completes the automatic layout of the core logic which might be similar to the following one
Figure 5. The automatically generated layout of the core logic.
Verifying the IC layout using the schematics (LVS)
Although the automatic tools performed the layout in Correct by Construction mode, it is always safer to verify the layout for correctness in terms of both layout design rules and connectivity to insure consistency between the various tools used. This establishes a system of "checks and balances" that increases the overall confidence in the design.
First we check for layout design rule errors using ICrules, then we verify the layout by double-checking it against the transistor level representation of the logic schematics. This procedure is very similar to earlier tutorials.
Step 1: Check Layout Design Rules
From the main ICstation palette select ICrules, then select Check from the ICrules palette. A prompt box will appear at the lower left of the screen. Click on OK to proceed with the check. Optionally, if you are using the ADK Edit menu, you can use Drc->Check.
Step 2: Fix any Design Rule Errors
When the check is complete, design rule errors in the layout will be reported in the message bar at the bottom of the ICstation window. The first one can be shown by selecting "First" in the palette (or DRC->First in the ADK Edit palette). The rest can be viewed by clicking on "Next".
For example, for our design we will get the following message:
”DRC completed. Total RuleChecks: 80; Total Results 26; Total original geometries 5000; ....”.
This means that there are 26 DRC errors. By selecting “First” in the IC Rules palette you will get the following:
“[Current DRC] Result 1 of 26 in Rule check bad_port: Port must be completely covered with Metal.”.
The autorouter failed to cover completely the ports with the respective metal layers (a very thin strip is missing). If you inspect layout you will see that for all ports we have two polygons implemented Metal1 and Metal1.port layers or in Metal2 and Metal2.port layers. There is no overlapping between the two, so you should cover Metal1.port or Metal2.port polygons with Metal1 or Metal2 shapes. To do this, select Easy Edit palette and Add Objects subsection and fix all ports (26 in this case). Repeat the DRC check; you should get 0 DRC errors.
Step 3: Layout versus Schematic test (LVS)
Verify the layout for consistency with the transistor level schematic of the design. Go back to the main ICstation palette and selecting the ICtrace(M) (mask level LVS) option. Click on LVS in the ICtrace(M) palette. In the dialogue box, enter the LVS viewpoint ($MGC_WD/work/ADDER_8/lvs) for "Source Name" and then click on the Setup LVS button. In the Setup LVS form, change the following items and click OK:
Ground Names: VSS GND (note that VSS and GND must be in separate boxes)
Recognize Gates: Yes
(If you’re already in the ADK Edit menu, you can go directly to these dialogue boxes by clicking on LVS)
Step 4: View the connectivity check results
When the check is complete, the bottom message bar will read "Mask results database loaded". To view the results, you can select Report -> LVS from the palette menu. Look for that magic smiley face. If a nasty X appears instead, go back and make certain that the LVS viewpoint has been properly setup and follow the above procedures again. When doing so, look for potential sources of discrepancies between the schematic and how the layout was generated.
Since the example is so simple, take a look at the layout to see how autorouter has handled the routing, size of VDD and GND ports and tracks, and how the cells are connected.
Step 5: Save the IC layout
Save the IC layout.
Step 6: Relative location of the ports
From the point of view of the structure of the complete integrated circuit it is important to know the relative location of the ports. Select/unselect (F2 key) connection to every port and obtain the relative port positions which might be similar to the following.
S(0) B(0) CI A(0) A(1) S(4) S(5) A(4) B(4)S(1)
B(1)
A(2)
Gnd
B(2) / B(5)
A(5)
Vdd
S(6)
A(6)
S(7)
S(3) B(3) A(3) S(2) B(6) B(7) A(7) Cout
Preparing for Fabrication - Adding Padframes in the schematics
The ports on your core logic are very small - typically a few square lambda in area. It is very difficult to bond a metal wire from an outside pin (a couple of mm's wide) to a port that is at the order of micrometres. Besides, the layout must also provide binding area for holding this wire onto the silicon cell. In order to prevent electrostatics damages, buffers and discharge diodes may be inserted into the ports to create tough I/O to interface.
This part is where you see metal pins (with decreasing width) drawing from outside I/O to the silicon layout in many layout photos.
Step 1: Generate symbol for your core logic
You need to generate a symbol for each piece of core logic (component) that you want to use. You will also need a completed IC layout for each component for which you have a symbol. These can be SDL or standard cell designs or a combination of both. Since we have already created the layout, we should create a symbol for the example by starting design architect in the design directory (as working directory), open the schematic, then Miscellaneous -> Generate Symbol. Make sure you click Yes on "Replace existing?". Leave all default options.
Check the symbol. Save the symbol. Close all symbol windows and schematic windows.
Step 2: Create new schematic
Now open a new schematic.
Change the component name to "final". Click on "Options" and click "New Sheet". OK all the forms and an empty schematic window will open. Use "Choose Symbol" on the palette to bring in the design part(s) and wire them together if necessary. In this example, choose adder (since we don't have any other logic to wire up). You need to add the phy_comp property (string) to the symbol. The value of phy_comp needs to be the name of the IC cell that you created. Select the symbol in your schematic and hit RMB (Right Mouse Button) and choose Properties -> Add. “New Property Name” is "phy_comp", Property Value is "adder", “Property Type” is "String". OK the form and choose any location to show this value.
Perform a check -> sheet and just ignore the unconnected pin warnings. Save the schematic.
In the ADK Library menu choose the pads to use from the appropriate library for your technology. Based on the technology, there may be different types of pads available. You can only use one set of technology pads and it must agree with the technology of your design. In this case, choose AMI 0.5.
Step 3: Add pads
Insert 17 "In" pads for the inputs ( A(7-0), B(7-0), Cin). Connect the DataIn pin of the pads to your input ports. Insert a "Out" pads for the outputs. Connect the DataOut pin of the pad to your output port. Insert 3 Vdd pads and 3 Gnd pads into the schematic for power and GND connections. Connect together all Vdd pads and all Gnd pads. No need to wire them up to your logic.