COEN6511 LECTURE 3

LONG CHANNEL MODEL

The nmos transistor:

There exist three regions of operation for an NMOS transistor. The same principle applies for a PMOS transistor, only that the polarity changes.

/ / Transistor cut-off
(*1) / / Triode region (linear)
(*2) / , / Saturation region (constant)
*3

1. Cut-Off Region:

VGS < VT

• No Inversion or Weak Inversion

• IDS = leakage current or sub-threshold current

•

2. Linear Region:

VGS > VT, and VDS < VGS-VT

• Channel surface is inverted

• Output current depends on VGS and VDS

•The relationship between IDS and VDS is almost linear

3. Saturation Region:

VGS > VT, and VDS VGS-VT

  • Voltage across channel tends to remainconstant
  • The current IDS saturates with very weak dependence on VDS
  • λ= channel length modulation parameter typical values 0.1 to 0.01V-1

For both cases of linear and saturation:

Effect of W: As W increases, Ids increases,

Effect of Temperature:Ids decreases since µ decreases.

For the pmos transistor the following relations hold.

VDSP>VGSP -VTP

VDSP <VGSP-VTP

KP=(W/L)K’P

Conductance in Linear & Saturation Regions:

Resistance of channel = =

as is very small

*3. Channel Modulation Factor

Similarly for the saturation region

(neglecting channel modulation effect)

If the channel length modulation is not neglected, then

Conductance=Resistance =

Conclusion: In saturation region, resistance between Drain and Source is usually a high value.

FAN-OUT RELATIONSHIP

Time constant = RC

R is resistance of Channel and C is capacitance of input

where

Conclusion

  1. Time constant is proportional to

For the case that two inputs are in parallel,

ie. You need twice the time !

  1. For CMOS technology, the time constant is proportional to the capacitances being charged.

SHORT CHANNEL MODEL

In the short channel model, two factors dominate the behavior of the model; Velocity saturation and mobility degradation.

TOH’S MODEL

In the Saturation region,for

In the Linear region,for

In the Saturation region, , ,

Conclusion:

•Short channel models are less dependent on L

•Difficult for first hand analysis

DESIGN OF LOGIC FAMILIES

Some desirable characteristics to have:

  1. Low power dissipation
  2. High noise margin (Equal high and low margins)
  3. High speed
  4. Low area
  5. Low output resistance
  6. High input resistance
  7. Reliability, Ease for testing
  8. Low cost
  9. High fan-out
  10. Low fan-in

Other important factors are:

  1. Single power supply
  2. System must have regenerative property
  3. System must possess directivity
  4. Rail-to-rail output switching

Regenerative Property

Directivity Property

Change needs to be propagated in one direction only. This is very difficult to achieve as there is always coupling and feedback. We will be looking for a circuit with minimum feedback or coupling in the system.

IDEAL INVERTER VOLTAGE TRANSFER CHARACTERISTIC (VTC)


REAL INVERTER VTC


CMOS INVERTER

A CMOS inverter has the following attributes:

  • They are simple circuits and hence has minimum silicon area
  • They are in a steady state most of the time and as such draw minimum power
  • They have well defined Vout levels

Regions of operation of the inverter:

In the steady state regions either transistor is off, hence no direct path between Vdd and ground as shown below.

In region A, pmos is in linear region while nmos is cut off. Current will not flow to ground but the pmos is on giving full Vdd at the output. Vout=Vdd.

In region B, PMOS linear, NMOS saturation: ignoring modulation effect.

Equate the two and solve for Vo

Can be changed as design parameter

Move to region C, Both NMOS and PMOS are in saturation.

Idsn= -Idsp hence equating and manipulating

To obtain the best switching point, the gate threshold voltage (Vin=Vout at VTC) has to be Vdd/2

If =1, Vin = Vdd/2 This is our design criterion hence, manipulating the expression to obtain Wn and Wp:

, Assume Ln=Lp, Coxn=Coxp

or , on CMOSIS 4B
Conclusion:

This means that we need to make Wp three times greater than Wn to get switching around Vdd/2. In practice, we use Wp = 2 x Wn. (Due to saving in area and also due to the fact that the variation of VTC around Vg is not much.). As we make Bn> Bp the VTC curve moves to the left and vice versa as shown below:

EFFECT OF TEMPERATURE

An increase in temperature results in a decrease in mobility and a drop in current.

An increase in temperature results in a decrease of the Threshold Voltage Vt.

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