Lesson-10 Libraries in VHDL

We need to declare a list of libraries that will be required by the compilers. These libraries contain the packages where various kind of type declarations & their definition, functions, procedures etc are declared and defined. Some of the Libraries in VHDL fall under the following categories:

  1. STD Library
  2. IEEE Library
  3. Work Library
  4. User Defined Library

STD library contain the definitions of the standard data types and some information about the text and file handling.

IEEE library is an improvement over std library and contain many new definitions and supported operations. VHDL has the standard and non-standard packages in the library of the syntheses/simulation software. Work library is automatically created when a new design is created and is a place holder for all the design files.User is also free to create theirown user defined library and packages.

The IEEE and STD libraries and the packages associated are given in the following table:

LIBRARY / PACKAGE / Definition given for / Definition of operators
Library std / Package standard / Basic VHDL types such as BOOLEAN, BIT, BIT_VECTOR, INTEGER, NATURAL, POSITIVE, REAL, TIME, DELAY_LENGTH etc / Related logical, arithmetic, comparison and shift operators
Library ieee / Package std_logic_1164 / Nine valued STD_ULOGIC and its resolved type STD_LOGIC / Only logical operations and some type conversion functions
Package numeric_std / Numeric type SIGNED and UNSIGNED, having STD_LOGIC as the base type / Logical, arithmetic, comparison, shift operator and some type conversion functions
Non Standard Packages
(provided by EDA vendors as sharewares) / Package std_logic_arith / Numeric type SIGNED and UNSIGNED, having STD_LOGIC as the base type / arithmetic, comparison, shift operator and some type conversion functions. This package is partially equivalent to numeric_std
Package std_logic_signed / STD_LOGIC_VECTOR as if it were SIGNED / Arithmetic, comparison and some shift operators for STD_LOGIC_VECTOR as if it were SIGNED
Package std_logic_unsigned / STD_LOGIC_VECTOR as if it were UNSIGNED / Arithmetic, comparison and some shift operators for STD_LOGIC_VECTOR as if it were UNSIGNED
User defined Libraries / User defined Packages / Inbuilt or User Defined

The procedure to declare a user defined library is given below:

Step-1:

Open a new file in the project, Select VHDL Library, Type the name of the Library, Select the location where you want to save the library

Check Add to Project and click Next. And then click Finish on the next scree.

Step-2

Click open a new source file. Select VHDL Package, type the file name, check Add to Project and click Next.

Create a VHDL module (e.g. and_gate) with the following code:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

packagemy_pkg is

TYPE data_bus is array (7 downto 0) of std_logic_vector(2 downto 0);

Type my_memory is array (0 to 3) of integer;

constant DATA: my_memory:= (000, 001, 010, 011);

endmy_pkg;

package body my_pkg is

endmy_pkg;

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Step-3

Click Libraries

Click work library in library pane

Click on + to explore work library

Right click on my_pkg and you see a pop up appearing as shown in screen shot.

Click Move to Library…….

Step-4

In the Move to Library window that opens, select to which Library (here it is my_lib) and click OK

The file and_gate will then move from work library to the new library my_Lib.

Step-5

Finally the package file my_pkg is now available in library my_lib

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Now we will use the type declarations made in the package my_pkg in the following VHDL code

library IEEE;------include IEEE library------

use IEEE.STD_LOGIC_1164.ALL;

LIBRARY my_lib;------include user defined library------

usemy_lib.my_pkg.all;------use user defined package------

useieee.std_logic_unsigned.all;

entity adds is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

s : out STD_LOGIC_VECTOR (2 downto 0);

cr : out STD_LOGIC);

end adds;

architecture Behavioral of adds is

signal plus : std_logic_vector (3 downto 0);

begin

plus <= '0' & a + DATA(0);--DATA is declared in my_pkg package

s <= plus(2 downto 0);

cr <= plus(3);

end Behavioral;