Title of the Paper – Template for IPFA 2018
Author 1, Author 2, Author 3, and Author 4*
1Department of ABC, XYZ University, 27 GHI Road, City Name, Pin Code, Country.
2Department of LMN, RST Institute of Technology, City Name, Pin Code, Country.
*Phone: +65-3-57121-57 Fax: +65-3-57121-79 Email:
Abstract-IGZO TFTs with gate/drain-offset lengths (LGDO) were fabricated with film-profile-engineering method and studied by 2-D numerical simulation. Gm of the fabricated devices decreases and VBD increases with increasing LGDO, Vth and SS remain relatively unchanged and VBD of ~80V are obtained with LGDO of 0.3μm. Output characteristics with VD up to 50V are also demonstrated, evidencing the capability for high-voltage operation.
Keywords – Adhesion, Defect clustering, Hexagonal boron nitride, Soft breakdown, Thin film transistors.
I. Introduction
Recently the potential of IGZO TFTs had been demonstrated for the construction of BEOL-transistors/circuits for I/O voltage-bridging between CMOS devices (low voltage) and peripheral devices (high voltage) such as displays and home electronics [1] – [4]. This application demands devices with compatibility to the BEOL processes, good mobility, and high on/off ratio, and high VD endurance. Although IGZO TFTs can meet most of the above requirements, the lack of a sufficiently high breakdown voltage (VBD) limits the capability of high-voltage operations. To increase the VBD of the devices, a structure with a gate-to-drain channel offset was proposed [2]. In this work, we fabricated devices with a gate-to-drain offset of varied lengths (LGDO) using a film-profile engineered (FPE) method proposed previously [5] and study the impact of the LGDO on device performance. Here we further investigate the impact of increasing LGDO on TFT characteristics and structures. High voltage operation of FPETFTs is evaluated for BEOL I/O voltage-bridging applications.In addition, we use a 2-D simulation to study and analyze the physics and electrical properties of devices.
II.EXPERIMENTS
The cross-sectional and top views of the IGZO FPETFTs with gate/drain-offset are shown in Figs. 1(a) and (b), respectively. As for the fabrication, first, a 100 nm-thick wet oxide and a 300 nm-thick SiNX were deposited sequentially on a Si wafer by low-pressure chemical vapor deposition (LPCVD). Then, a 100 nm-thick TiN was deposited by sputtering and then patterned as the gate electrode. A 400 nm-thick TEOS oxide and a 200 nm-thick TiN serving as the sacrificial oxide and hardmask (HM), respectively, were deposited sequentially by plasma-enhanced chemical vapor deposition (PECVD) and sputtering. After that, the top TiN HM was patterned to define the S/D regions of the devices, followed by stripping off the sacrificial oxide. Next, a nominally 40 nm-thick TEOS oxide was deposited as the gate dielectric by PECVD. Afterwards the IGZO channel with nominal thickness of 50 nm was deposited by RF magnetron sputter at room temperature (RT). After the formation of S/D electrodes by thermal evaporation of a 120 nm-thick Al at RT, a PECVD oxide was used as the passivation layer to cap the active region of the device. The contact holes were then formed by reactive ion etching. Finally, an annealing was performed at 300°C for 30 mins in vacuum ambient.
Fig. 1 (a) Cross-sectional view and (b) top view of the IGZO FPETFT with gate/drain-offset.
Fig. 2 shows the transmission electron microscopy (TEM) and scanning electron microscope (SEM) images of TFTs with drain-overlap and drain-offset structure (LGDO = 0.3 μm). In Fig. 2(a), it can be seen that the drain and gate electrodes have an overlap region of 0.3μm in length. In Figs.2 (b) and (c), the gate is intentionally offset from drain electrode for 0.3μm. The thicknesses of the channel and gate oxide layers over the bottom gate are non-uniform and in a concave shape, owing to the shadowing nature of the suspended HM [5-7]
Fig. 2 (a) and (b) TEM image of TFT with drain-overlap and drain-offset structure (LGDO=0.3 μm).
III. Results and discussion
Fig. 3 compares the transfer characteristics between drain-overlap and drain-offset TFTs with different LGDO. The inset shows details about the on-current comparisons of the TFTs in which the reduction of the on-current with increasing LGDO can be observed clearly, especially when the LGDO is increased to 0.3 μm. In Fig. 4, the output characteristics measured at VG-VTH = 4 V for the devices also reveal a similar trend [8] – [15]. However, the variation in the operation of subthreshold regions has no distinct pattern with increasing LGDO, as can be seen in Fig. 3.
Fig. 3 Transfer characteristics of IGZO FPE TFTs with different LGDO.
Fig. 4 Output characteristics between drain-overlap and drain-offset TFTs with different LGDO.
Typical gate currents (IG) for devices with various LGDO measured as a function of drain voltage (VD) under VG = VS = 0V are shown in Fig. 5. VBD data of TFTs with different LGDO are extracted as the VD when |IG| rises to exceed 1×10-9 A. The noisy IG characteristics as VGVBD indicate the soft breakdown (BD) conduction.For the drain-overlap devices with LGDO of -0.3 μm, VBD values are slightly larger than 20 V. As the LGDO increases, the VBD increases monotonically, and values of ~80 V are obtained at LGDO of 0.3 μm.
Fig. 5 IG as a function of VD measured at VG=VS=0 V.
The plots of extracted TFT parameters (VBD, transconductance (gm), subthreshold swing (SS), and Vth) as a function of LGDOand the variations of these parameters are shown in Fig. 6. While Vth and SS remain relatively unchanged at around 1 V and 200 mV/decade, respectively, a decrease in gm and an increase in VBD with increasing LGDO are evident [16] – [22]. However the extracted gm ~ 4.5μS with LGDO = -0.3μm decreases to ~ 2μS with LGDO = 0.3μm. The LGDO is thus a trade-off parameter between on-state performance and the operation voltage.
Fig. 6 Extracted TFT parameters (VBD, gm, SS, and Vth) as a function of LGDO.
Fig. 7 depicts the output characteristics for high voltage operation of a TFT with LGDO = 0.3 μm. Maximum VD= 50 V can be applied at VG-VTH = 2~6 V in this evaluation. The low IG is also shown in this figure confirming that the BD of device is not occurred. Nevertheless, a hump phenomenon in ID is observed as VG and VD is sufficiently high. Its root cause is under investigation.
Fig. 7 Output characteristics of IGZO TFT with LGDO = 0.3 μm with VD =50V.
Fig. 8 compares the transfer characteristics at VD = 0.1V and 1V between simulated and measured TFTs with LGDO of 0.3 μm.The 2-D simulated resultsagreed with the measured curves very well except for predicting the measured off-state current, which is the minimum current resolution of semiconductor parameter analyzer. The parameters used in 2-D simulations are listed in Table I.
Fig. 8The measured and simulated transfer characteristics of IGZO FPETFTs withLGDO = 0.3μm.
Table I - Parameters used in 2-D simulations
Symbol / Value / Unit / DescriptionNTA / 1×1018 / cm-3 / Shallow acceptor-like trap DOS
WTA / 0.01 / cm-3/eV / Shallow acceptor-like trap slope
NGA / 1×1016 / cm-3 / Deep acceptor-like trap DOS
EGA / 0.6 / eV / Deep acceptor-like trap slope
WGA / 0.1 / cm-3/eV / Deep acceptor-like trap mean energy
EG / 3.2 / eV / Band gap
X / 4.16 / eV / Electron affinity
εr / 10 / Dielectric constant
μ / 20 / Electron mobility
ND / 1e18 / cm-3 / Doping concentration
Fig. 9 shows thesimulation results on the (a) electric field (E) and (b) electron concentration (ne) for the IGZO FPETFTs operated at on-state case (VD = 1 V and VG = 6 V).The most of E is applied to the center of device in SiO2 and the small portion of E applied to the a-IGZO layer induced the ne accumulated at the a-IGZO/SiO2 interface. It can be noted that the E is not distributed in the gate-to-drain offset region and the number of ne is thus smaller than that of center region, which indicates that the offset region has high resistance and degrades the device performance [23, 24].
The 2-D simulation results on the (a) E and (b) electric temperature (Te) for the IGZO FPETFTs whose BD occurred (VD = 80 V and VG = VS = 0 V) are shown in Fig. 10.From the E contour map, the distribution of E is concentrated at the drain-side of devices in the SiO2 and the BD location is very likely close to the edge of the drain electrode because of enhanced strength of E (high VD) [25]. Moreover, the E is penetrated toward the direction of gate electrode and a lot of electron would be accelerated to become the hot electrons whose temperature is above 1×104 K, as shown in Te contour map.
Fig. 92-D simulation results on the (a) E and (b) ne for the IGZO FPETFTs operated at VD = 1 V and VG = 6 V.
IV. Conclusion
We have fabricated IGZO FPETFTs with various gate/drain-offset lengths. Although Vth and SS of devices show weak dependence of LGDO, gm decreases and VBD increases with increasing LGDO. VBD of ~80 V are obtained for devices with LGDO of 0.3 μm. Output characteristics with VD up to 50 V are successfully demonstrated, evidencing the capability of the IGZO FPETFT for HV operation.Finally, the detailed device characteristics have been well understood from the 2-D simulation.We have fabricated IGZO FPETFTs with various gate/drain-offset lengths. Although Vth and SS of devices show weak dependence of LGDO, gm decreases and VBD increases with increasing LGDO. VBD of ~80 V are obtained for devices with LGDO of 0.3 μm. Output characteristics with VD up to 50 V are successfully demonstrated, evidencing the capability of the IGZO FPETFT for HV operation. Finally, the detailed device characteristics have been well understood from the 2-D simulation.
Acknowledgment
This work was sponsored in part by the National Natural Science Foundation of Singapore, under Grant No.ABC-123445-UYT.
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