Project 1:
INPUT: <input>.c , #INPUT PORTS, #OUTPUT PORTS
e.g., diffeq.c, 3, 1
//assign inputs randomly to ports
Read(RP1, x)
Read(RP2, dx)
Read(RP3, u)
Read(RP1, a)
Read(RP2, y)
While(x<a)
{
t1=u*dx
t2=3*x
t3=3*R6
t4=t1*t2
t5=t3*dx
t6=u-t4
u=t6-t5
y=y+t1
x=x+dx
}
Output(OP1, y)
Pro1
Input constraints:
Only integer operations
Simple if-else(no nested)
1D loop
No array ,Pointer ,structure and node
Command to get Basic blocks
gcc –Fdump-tree-all
gcc –Fdump-tree-cfg
Output format
Control flow
B1 1 C1
C1 2 TB2 FB3
B2 1 C1
B3 0
Operations:
<Basic Block No, (Operation type), (operation representation)
Operations type: Read from port, Assignment, Write to port operation
Operation Representation:
For Read: (port no, input variable, input width)
For Write: (port no, output variable, output width)
For Assignment:
(Target Var, Variable width), (left operand, width of left operator),Operator,(right operand, Variable width)
B1, R, (RP1, x,16)
B1, R, (RP1, dx,8)
B1, R, (RP2, u,16)
B1, R, (RP2, a, 16)
B1, R, (RP2, y, 16)
C,A, (c,1 ), ( x,32), , (a, 16)
B2, A,(t1,24),(u,16), *, (dx,8)
B2, A, (t2,24),(3,8), *, (x,16)
B2, A, (t3,24),(3,8), *, (y,16)
B2, A, (t4,32),(t1,24), *, (t2,24)
B2, A, (t5,32),(t3,24), *, (dx,8)
B2, A, (t6,32),(u,16), -, (t4,16)
B2, A, (u,32),(t6,32), -, (t5,32)
B2, A, (y,32),(y,16), +,(t1,24)
B2, A, (x,32),(x,16), +,(dx,8)
B3, O, (OP1, y, 16)
Project 2:
Assigning time stamp to each operation
<Basic Block No>, Time Stamp, (Operation type), (operation representation)
Output
B1, 1, R, (RP1, x, 16)
B1, 1, R, (RP1, dx, 4)
B1, 1, R, (RP2, u, 16)
B1, 1, R, (RP2, a, 16)
B1, 1, R, (RP2, y, 16)
C1,1, A, (c, 1 ), ( x, 32), <, (a, 16)
B2,1, A, (t1, 24), (u, 16), *, (dx, 4)
B2, 1, A, (t2, 24), (3, 2), *, (x, 16)
B2, 2, A, (t3, 24), (3, 2), *, (y, 16)
B2, 2, A, (t4, 32), (t1, 24), *,(t2, 24)
B2, 3, A, (t5, 32), (t3, 24), *, (dx, 8)
B2,3, A, (t6, 32), (u, 16), -, (t4, 16)
B2,4, A, (u, 32), (t6, 32), -, (t5, 32)
B2, 2, A, (y, 32), (y, 16), +, (t1, 24)
B2,1, A, (x, 32), (x, 16), +, (dx, 4)
B3, 1, O, (OP1, y, 16)
Project 4:
Register and Functional Unit Allocation and Binding:
<Specify Registers>
<Register >, <Register Width>
R1, 32
R2, 48
R3, 17
R4, 32
R5, 16
R6, 16
R7, 2
R8, 4
R9, 1
<Specify FUs>
FUNCTIONAL UNIT, ( Operation type#1,Operation type#2,..), (out_width, in1_width, in2_width)
ADDER1, (ADD, SUB), (48, 32,24)
MULT1,(MULT), (32, 24, 16)
MULT2,(MULT), ( 48, 24, 48)
COMP1, (LT), (1, 17,16)
<Specify RT operations>
(Target Var, Variable width), (Source Var1, Variable width),(FU, Operation Type) ,(Source Var2, Variable width)
B1, 1, R, (RP1, R3, 16)
B1, 1, R, (RP1, R8, 4)
B1, 1, R, (RP2, R4, 16)
B1, 1, R, (RP2, R5, 16)
B1, 1, R, (RP2, R6, 16)
C1,1, A, (R9, 1 ), ( R3 , 17), (COMP1,LT), (R5, 16)
B2,1, A, (R1, 32), (R4, 16), (MULT1,MULT), (R8, 4)
B2, 1, A, (R2, 48), (R7, 2), (MULT2,MULT), (R3 , 17)
B2, 2, A, (R1, 24), (R7, 2), (MULT1,MULT), (R6, 16)
B2, 2, A, (R2, 48), (R1, 24), (MULT2,MULT), (R2, 48)
B2, 3, A, (R1, 32), (R1, 24), (MULT1,MULT), (R8, 4)
B2, 3, A, (R2, 48), (R4, 16), (ADDER, SUB), (R2, 16)
B2,4, A, (R4, 32), (R2, 48), (ADDER, SUB), (R1, 32)
B2,2, A, (R6, 32), (R6, 16), (ADDER, ADD), (R1, 24)
B2, 1, A, (R3, 17), (R3, 16), (ADDER, ADD), (R8, 4)
B3, 1,O, (OP1, R6, 16)
Project 5:
Data Path and Controller Generation
#Data path
<Specify Registers>
R1, 32
R2, 48
R3, 17
R4, 32
R5, 16
R6, 16
R7, 2
R8, 4
R9, 1
<Specify FUs>
ADDER1, (ADD, SUB), (48, 32,24)
MULT1 , (MULT), (32, 24, 16)
MULT2,(MULT), ( 48, 24, 48)
COMP1, (LT), (1, 17,16)
<Specify RT operations>
B1, 1, R, (RP1, R3, 16)
B1, 2, R, (RP1, R8, 4)
B1, 1, R, (RP2, R4, 16)
B1, 2, R, (RP2, R5, 16)
B1, 3, R, (RP2, R6, 16)
C1, 1, A, (R9, 1), ( R3 , 17), (COMP1, LT), (R5, 16)
B2, 1, A, (R1, 32), (R4, 16), (MULT1, MULT), (R8, 4)
B2, 1, A, (R2, 48), (R7, 2), (MULT2, MULT), (R3 , 17)
B2, 2, A, (R1, 24), (R7, 2), (MULT1, MULT), (R6, 16)
B2, 2, A, (R2, 48), (R1, 24), (MULT2, MULT), (R2, 48)
B2, 3, A, (R1, 32), (R1, 24), (MULT1, MULT), (R8, 4)
B2, 3, A, (R2, 48), (R4, 16), (ADDER, SUB), (R2, 16)
B2, 4, A, (R4, 32), (R2, 48), (ADDER, SUB), (R1, 32)
B2, 2, A, (R6, 32), (R6, 16), (ADDER, ADD), (R1, 24)
B2, 1, A, (R3, 17), (R3, 16), (ADDER, ADD), (R8, 4)
B3, 1, O, (OP1, R6, 16)
<Specify MUX>
<MUX Name> <Input of MUX>, <Output of MUX>, <Control signal in order>
<M1<R1,R4,R7<MULT1<00,01,10>
<M2<R8,R6<MULT1<0,1
<M3<R1,R7<MULT2<0,1
<M4<R2,R3<MULT2<0,1>
<M5<R2,R3,R4,R6<Adder1<00,01,10,11>
M6<R1, R2, R8<Adder1<00,01,10
<M7<MULT2,ADDER1<R2<0,1>
#Controller
INPUT: input CFG
Control flow
B1 1 C1
C1 2 T B2 F B3
B2 1 C1
B3 0
OUTPUT:
Controller FSM:
B11 1 B12
B12 1 B13
B13 1 C1
C1 2 T B21 F B31
B211 B22
B22 1 B23
B23 1 B14
B14 1 C1
B31 1 B32
B32 0
Control Signals:
CS for MUX in order:
(#MUX,#Controlbits)
(M1, 2), (M2, 1),(M3, 1),(M4, 1),(M5, 2),(M6, 2),(M7, 1)
CS for Reg enable in order:
(1,1,1,1,1,1,1,1,1)
CS for FU in order:
(FU, #Control bits)
(ADDDER, 1), (MULT1, 0), (MULT2, 0), (COMP1,0)
B11:
(CS for MUX)(CS for Regen) (CS for FU)
(0000000000)(001100000)(0)
B12:
(0000000000)(000010010)(0)
B13:
(0000000000)(000001000)(0)
C1:
(0000000000)(000010010)(0)
B21:
(0101101100)(111000000)(0)
B22:
(1010011000)(110001000)(0)
B23:
(0000000001)(110000000)(1)
B24:
(0000000000)(000100000)(1)
B31:
(0000000000)(000001000)(0)