Tallinna Tehnikaülikool
Infotehnoloogia teaduskond
Arvutitehnika instituut
Digitaaltehnika õppetool
Laboratoorne töö 2
Aruanne aines
Riist- ja tarkvara koosdisain
Töö sooritasid: Vadim Pesonen 020613
Maksim Gorev 020281
Juhendaja: Prof. Kalle Tammemäe
Tallinn 2009
The aim of the work is to implement a simple start/stop/reset timer using the XESS development board and Xilinx Picoblaze soft processor.
In terms of hardware and software, the design was partitioned as follows:
- Every second the hardware generates a pulse which is connected to the interrupt input of the processor
- The software runs a counter with a value range from 0 to 9 and send this value to the output port in binary form
- The hardware performs the conversion from binary to decimal and displays the value on the 7-segment indicator
The hardware part
Pulse generation, start, stop and reset functions
The hardware generates a short pulse every approximately second. The following Verilog code best describes how this is done:
always @ (posedge clk or posedge reset)
begin
if (reset)
divider <= 0;
else if (divider == 49_999_999)
divider <= 0;
else if (start)
divider <= divider + 1;
end
//
The incoming clock signal clk has a frequency of 50MHz. A counter which counts to 50 million will overflow every second. The counter only counts when signal start is high. Every time the button SW2 on the board is pressed, the value of the signal (it is registered) toggles. This implements the start/stop function. The following code illustrates this:
always @ (posedge button_deb or posedge reset)
begin
if (reset)
start <= 1'b0;
else
start <= !start;
end
//
The signal button_deb acts as a clock in this case. Since it is connected to a mechanical button, is has to be filtered, or debounced. This is done in the following way:
always @ (posedge clk or posedge reset)
begin
if (reset)
deb <= 0;
else
deb <= {deb[13:0],button};
end
//
always @ (posedge clk or posedge reset)
begin
if (reset)
button_deb <= 1'b0;
else if (deb == 15'b11111_11111_11111)
button_deb <= 1'b1;
else if (deb == 15'b00000_00000_00000)
button_deb <= 1'b0;
end
//
First, on every rising edge of the 50Mhz clock the value from the button is pushed into a 15-bit shift register. Once the register is all ones, then resulting value is also a 1. If the register is all zeros, then the resulting value is also a zero. Otherwise, the value does not change. This gives a good filtering property.
In order to produce a pulse, the signal int is assigned high when the counter possesses its last two values before zeroing. This produces a pulse of a 2 clock cycle duration, as shown below:
assign int = ((divider == 49_999_998) || (divider == 49_999_999));
The reset function is implemented by clearing all counters/registers.
Output value decoding
The processor provides a 4-bit binary code of the value to be displayed. It is decoded in the following way:
always @ (code)
begin
case (code)
// abc_def_g
0:leds = 7'b111_111_0;
1:leds = 7'b011_000_0;
2:leds = 7'b110_110_1;
3:leds = 7'b111_100_1;
4:leds = 7'b011_001_1;
5:leds = 7'b101_101_1;
6:leds = 7'b101_111_1;
7:leds = 7'b111_000_0;
8:leds = 7'b111_111_1;
9:leds = 7'b111_101_1;
default:
leds = 7'b000_000_1;//something is wrong
endcase
end
//
The software part
Software part was designed as follows:
- PicoBlaze gets interrupt request every second from hardware.
- During interrupt service routine (ISR) current counter value is comared to decimal value 9. If they are equal – counter resets.
- Otherwise SW increments counter value
- After that it outputs this value in binary to hardware
Assembler program is using 2 register to store counter value and decimal value 9(it can be defined as a constant, but for study purposes were put into register) and 2 procedures to increment and reset counter.
When processor waiting for interrupt request it simly permanently outputs counter value to harware in main loop. When interrupt request takes place programm comares 2 registers and if they are equal jumps to procedure which set counter register to 0, otherwise if they are different another procedure increments counter. After that interrupt requests are enabled and program exits ISR and jumps to main loop.
To write the program pBlazIDE36 software were used to enter code, test and compile a code into VHDL instruction ROM.
Summary
This lab taks have given us the common understanding of usage of Picoblaze development tools, it's hardware interface, programm execution and interrupt handling possibilities. The goal of building the stopper clock using PicoBlaze processor was successfuly reached.