BH
#include "xparameters.h"
#include "stdio.h"
#include "xbasic_types.h"
#include "xiic_l.h"
#include "xio.h"
#include "xuartlite_l.h"
#include "platform.h"
#define XPAR_XPS_IIC_0_BASEADDR 0x81600000
#define XPAR_RS232_UART_1_BASEADDR 0x84000000
#define DECODER_ADDR_W (0x42 >1) //Read: 0x41, Write: 0x40
#define DECODER_ADDR_R 0x41
#define GPO_RESET_DECODER 0
#define GPO_RESETS_OFF 1
#define GPO_RESET_IIC 3
int iic_test();
void main_memu(void);
void Reset_xup_decoder(void);
static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,unsigned ByteCount, u8 Option);
int w;
struct VideoModule { Xuint8 addr; Xuint8 config_val; Xuint8 actual_val; };
void configDecoder(struct VideoModule *decoder, int config_cnt );
#define DECODER_SVID_CONFIG_CNT 17
struct VideoModule decoder_svid[] = { { 0x00, 0x06, 0 }, { 0x15, 0x00, 0 }, { 0x27, 0x58, 0 }, { 0x3a, 0x12, 0 }, { 0x50, 0x04, 0 }, { 0x0e, 0x80, 0 }, { 0x50, 0x20, 0 }, { 0x52, 0x18, 0 }, { 0x58, 0xed, 0 }, { 0x77, 0xc5, 0 }, { 0x7c, 0x93, 0 }, { 0x7d, 0x00, 0 }, { 0xd0, 0x48, 0 }, { 0xd5, 0xa0, 0 }, { 0xd7, 0xea, 0 }, { 0xe4, 0x3e, 0 }, { 0xea, 0x0f, 0 }, { 0x0e, 0x00, 0 } };
#define DECODER_COMP_CONFIG_CNT 17
struct VideoModule decoder_comp[] = { { 0x00, 0x04, 0 }, { 0x15, 0x00, 0 }, { 0x17, 0x41, 0 }, { 0x27, 0x58, 0 }, { 0x3a, 0x16, 0 }, { 0x50, 0x04, 0 }, { 0x0e, 0x80, 0 }, { 0x50, 0x20, 0 }, { 0x52, 0x18, 0 }, { 0x58, 0xed, 0 }, { 0x77, 0xc5, 0 }, { 0x7c, 0x93, 0 }, { 0x7d, 0x00, 0 }, { 0xd0, 0x48, 0 }, { 0xd5, 0xa0, 0 }, { 0xd7, 0xea, 0 }, { 0xe4, 0x3e, 0 }, { 0xea, 0x0f, 0 }, { 0x0e, 0x00, 0 } };
#define DECODER_CMPNT_CONFIG_CNT 13
struct VideoModule decoder_cmpnt[] = { { 0x00, 0x0a, 0 }, { 0x27, 0xd8, 0 }, { 0x50, 0x04, 0 }, { 0x0e, 0x80, 0 }, { 0x52, 0x18, 0 }, { 0x58, 0xed, 0 }, { 0x77, 0xc5, 0 }, { 0x7c, 0x93, 0 }, { 0x7d, 0x00, 0 }, { 0xd0, 0x48, 0 }, { 0xd5, 0xa0, 0 }, { 0xe4, 0x3e, 0 }, { 0x0e, 0x00, 0 } };
int main ()
{
print("-- Entering main() --\r\n");
iic_test();
print("-- Exiting main() --\r\n");
cleanup_platform();
return 0;
}
int iic_test()
{
Xuint8 ad7183_data[5]; //
Xuint8 ad7183_tmp[1];
unsigned ReceivedByteCount = 0;
int j=0;
ad7183_tmp[0] = 0x00; //reset sequence
ad7183_data[0] = 0x55;
ad7183_data[1] = 0x00;
ad7183_data[2] = 0x55;
ad7183_data[3] = 0x00;
ad7183_data[4] = 0xAA;
XIIC_RESET(0x81600000);
XIic_mSend7BitAddress(XPAR_XPS_IIC_0_BASEADDR, DECODER_ADDR_W, XIIC_WRITE_OPERATION);
print("\r\nXUP-V2Pro Video Decoder Expansion Board Video Pass Through Test ");
print("\r\nDetecting Video Decoder...\t");
//ReceivedByteCount =XIic_Send(XPAR_XPS_IIC_0_BASEADDR , DECODER_ADDR_W , ad7183_data, 5, XIIC_REPEATED_START);
ReceivedByteCount=SendData(XPAR_XPS_IIC_0_BASEADDR, ad7183_data, 5, XIIC_REPEATED_START);
if(ReceivedByteCount != 5)
print("No device detected!\r\n");
else
{
configDecoder(decoder_comp, DECODER_COMP_CONFIG_CNT);
print("Decoder detected! Configuring for composite video - default.\r\n");
main_memu();
}
return 0;
}//end of iic_test()
void main_memu(void)
{
char keyboard=0;
init_platform();
do {
print("\r\nMode Selection Menu ");
print("\r\n------\r\n");
print("1 - Program Composite Video Input Mode.\r\n");
print("2 - Program S - Video Input Mode.\r\n");
print("3 - Program Component Video Input Mode.\r\n");
print("q - Quit\r\n");
do {
keyboard = XUartLite_RecvByte(XPAR_RS232_UART_1_BASEADDR);
xil_printf ("%c \r\r\n", keyboard);
} while(( keyboard < '1' || keyboard > '3') & keyboard != 'q');
xil_printf ("%c \r\r\n", keyboard);
switch(keyboard) {
case '1':
Reset_xup_decoder();
configDecoder(decoder_comp, DECODER_COMP_CONFIG_CNT);
break;
case '2':
Reset_xup_decoder();
configDecoder(decoder_svid, DECODER_SVID_CONFIG_CNT);
break;
case '3':
Reset_xup_decoder();
configDecoder(decoder_cmpnt, DECODER_CMPNT_CONFIG_CNT);
break;
}
} while( keyboard != 'q' );
print("\r\nGoodbye.\r\n");
}
static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,unsigned ByteCount, u8 Option)
{
u32 IntrStatus;
/* Send the specified number of bytes in the specified buffer by polling
* the device registers and blocking until complete
*/
while (ByteCount > 0) {
/* Wait for the transmit to be empty before sending any more data
* by polling the interrupt status register
*/
while (1) {
IntrStatus = XIIC_READ_IISR(BaseAddress);
if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_ARB_LOST_MASK |
XIIC_INTR_BNB_MASK)) {
return ByteCount;
}
if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
break;
}
}
/* If there is more than one byte to send then put the next byte to send
* into the transmit FIFO
*/
if (ByteCount > 1) {
XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET,
*BufferPtr++);
}
else {
if (Option == XIIC_STOP) {
/* If the Option is to release the bus after the last data
* byte, Set the stop Option before sending the last byte
* of data so that the stop Option will be generated
* immediately following the data. This is done by clearing
* the MSMS bit in the control register.
*/
XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
XIIC_CR_ENABLE_DEVICE_MASK |
XIIC_CR_DIR_IS_TX_MASK);
}
/* Put the last byte to send in the transmit FIFO */
XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET,
*BufferPtr++);
if (Option == XIIC_REPEATED_START) {
XIic_mClearIisr(BaseAddress,
XIIC_INTR_TX_EMPTY_MASK);
/* Wait for the transmit to be empty before setting RSTA bit. */
while (1) {
IntrStatus =
XIIC_READ_IISR
(BaseAddress);
if (IntrStatus &
XIIC_INTR_TX_EMPTY_MASK) {
/* RSTA bit should be set only when the FIFO is completely Empty.
*/
XIo_Out8(BaseAddress +
XIIC_CR_REG_OFFSET,
XIIC_CR_REPEATED_START_MASK
|
XIIC_CR_ENABLE_DEVICE_MASK
|
XIIC_CR_DIR_IS_TX_MASK
| XIIC_CR_MSMS_MASK);
break;
}
}
}
}
/* Clear the latched interrupt status register and this must be done after
* the transmit FIFO has been written to or it won't clear
*/
XIic_mClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
/* Update the byte count to reflect the byte sent and clear the latched
* interrupt status so it will be updated for the new state
*/
ByteCount--;
}
if (Option == XIIC_STOP) {
/* If the Option is to release the bus after transmission of data,
* Wait for the bus to transition to not busy before returning, the IIC
* device cannot be disabled until this occurs.
* Note that this is different from a receive operation because the stop
* Option causes the bus to go not busy.
*/
while (1) {
if (XIIC_READ_IISR(BaseAddress) &
XIIC_INTR_BNB_MASK) {
break;
}
}
}
return ByteCount;
}
void Reset_xup_decoder(void)
{
int send_cnt = 0;
int wait_delay = 500000;
XIic_mWriteReg(XPAR_XPS_IIC_0_BASEADDR, XIIC_GPO_REG_OFFSET, GPO_RESET_DECODER); // reset to vid decoder
while(wait_delay)
{
wait_delay = wait_delay -1;
}
XIic_mWriteReg(XPAR_XPS_IIC_0_BASEADDR, XIIC_GPO_REG_OFFSET, GPO_RESETS_OFF); // set resets de - asserted
wait_delay = 5000000;
while(wait_delay)
{
wait_delay = wait_delay -1;
}
return;
} // end Reset_xup_decoder
void configDecoder(struct VideoModule *decoder, int config_cnt )
{
Xuint16 i;
Xuint8 send_data[2] = {0};
Xuint8 success = 1;
unsigned ReceivedByteCount = 0;
print(" Configuring Decoder...\t");
for( i = 0; i < config_cnt; i++ )
{
XIic_mWriteReg( XPAR_XPS_IIC_0_BASEADDR, XIIC_GPO_REG_OFFSET, GPO_RESET_IIC);
XIic_mWriteReg( XPAR_XPS_IIC_0_BASEADDR, XIIC_GPO_REG_OFFSET, GPO_RESETS_OFF);
send_data[0] = decoder[i].addr;
send_data[1] = decoder[i].config_val;
ReceivedByteCount =SendData(XPAR_XPS_IIC_0_BASEADDR , send_data, 2, XIIC_REPEATED_START);
if( ReceivedByteCount != 2 )
{
xil_printf("Error writing to address %02x\r\n", decoder[i].addr);
success = 0;
break;
}
}
if( success )
print("SUCCESS!\r\n");
}