C -302-701 Lab Project # 3
Note: From Lab 3 onwards, you must use std_logic type and not bit type
PART A
Flip-flops and Counters in Behavioral Style (4 points)
Model the JK flip-flop with PRESET and CLEAR as a state machine including an
undefined state (as discussed in class). Write complete VHDL code for it and simulate it.
(2)
Use this J-K flip-flop as a component in the BCD counter of Lab2 and simulate it (1)
Write behavioral code for the BCD counter without using any components and simulate it
(1)
PART B
Modelling Memory Chip (3 points)
Write VHDL behavioral style description of a RAM chip containing 16 locations
of 8 bits each. The chip has a 8-bit data bus(bidirectional) and a 4-bit address bus
which is an input. The other input pins are clock(CLK), clear(CLR) and
read/write (RW). When CLR pin is low, all memory locations are set to zero
asynchronously. When CLR is high, the chip will perform a synchronous ‘Write’
operation if RW is low and will perform a synchronous ‘Read’ operation if RW
is high. The entity description is as follows:
entity RAM is
generic(m:natural:=4,n:natural:=8);
port (clk,clr,rw:in std_logic; addrbus:in std_logic_vector(m-1 downto 0);
databus:inout std_logic_vector(n-1 downto 0));
end RAM;
Write the architecture in behavioral style and simulate it. First demonstrate the
memory clearing operation and then write some 8-bit values to 3 different locations
and read them back in a different order.
Extra Credit Part ( 1 point)
3. Modelling a Two’s Complement Device: (in behavioral style)
The 2’s complement of a signed number can be generated bit by bit with the
following algorithm: Scan the bits starting with the least significant bit. Copy
all the ‘0’s and the first ‘1’. Then invert all the remaining bits. This process
will generate the 2’s complement of the given number, which can be input to the
device one bit on each clock beginning with the least significant bit. The entity
description is as follows:
entity twoscomp is
generic (n:natural:=8);
port(x,clk,en:in std_logic;y:out std_logic);
end
When en is made high, the device should start working with the inputs being
applied on successive clocks x(0),x(1),....x(n-1). The device generates
y(0), y(1),...y(n-1) on successive clocks. If any more inputs are applied ,
they should be ignored. Note x and y are scalars with the index i in x(i)
meaning ith clock interval