Fermi-FET Technologyseminar Report 03

Fermi-FET TechnologySeminar Report ‘03

INTRODUCTION

Transistor scaling, a major driving force in the industry for decades, has been responsible for the dramatic increase in circuit complexity. Shorter gate lengths have required lower drain voltages and concurrently lower threshold voltages. Recent CMOS evolution has seen a dramatic reduction in operating voltage as transistor size is reduced. This was due to the maximum field limit on the gate oxide needed to maintain good long-term reliability. Proper selection of the gate material can produce low threshold transistors with off-state performance parameters equivalent to high threshold devices.

The Buried Channel Accumulation device, currently being used for p-type transistor processes has the Fermi level at a considerable depth from the gate thereby making it difficult to shut the device off. Attempts to bring the Fermi level up result in severe degradation of device performance. Need for optimization of existing BCA technology arose and Thunderbird Technologies, Inc. delivered! The ‘incredible’: Fermi-FET.

The Fermi-FET technology brings the Fermi level nearer to the gate. This technology merges the mobility and low drain current leakage of BCA devices as well as the higher short channel effect immunity of SCI devices. This paper highlights aspects of the technology in a non-mathematical presentation to give a sound general understanding of why the technology is the most promising avenue for advanced very short devices.

Fermi-FET technology can lead to significant improvement in circuit performance, layout density, power requirements, and manufacturing cost with only a moderate alteration of traditional MOSFET manufacturing technology. This technology makes use of a subtle optimization of traditional buried channel technology to overcome the known shortcomings of buried channel while maintaining large improvements in channel mobility.

Fermi-FET can optimize both the N-Channel and P-Channel devices with a single gate material, provided the work function is near the mid-range between N and P-type polysilicon. Materials that have been used in MOSFET technology with a suitable work function include Tungsten, Tungsten Silicide, Nickel, Cobalt, Cobalt Silicide, P-type Ge:Si and many others. There is about a 30% reduction in junction capacitance relative to traditional MOSFET devices. This fact alone gives a significant speed advantage to the Fermi-FET in large scale circuits. The total speed improvement produced by both the lowered threshold and lowered gate and junction capacitances is very substantial.

In order to illustrate the impact of lowered threshold voltages via work function engineering, the large-signal transient response of two inverter structures was simulated. A comparison of conventional CMOS and metal-gate Fermi-FET structures was performed. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET. The different delay characteristics are evident. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET

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The individual device DC characteristics were already well-known from the device simulations. For each inverter, the supply voltage was ramped up to Vdwith a delay sufficient to allow the circuit nodes to settle to their initial DC state with the input low. The input was then pulsed high, then low; again with a delay time long enough to guarantee all nodes reach steady state. The corresponding outputs obtained give a comprehensive view of the device performance as compared to the traditional technology and thus acts a primary assessment of the feasibility of the new technology in lieu of existing ones.

Figure (a)

The output of the mixed-mode simulations is shown in the figure. Even at 0.4 mm gate length the low threshold Fermi-FET is almost twice as fast as the MOSFET in this simple circuit.

Simple circuits such as this underestimate the benefit of the lowered capacitance associated with the source/drain junctions, but they virtually ignore the capacitance associated with the extended wiring in large circuits. The Fermi-FET is the emerging technology in the ever-expanding empire of electronics circuits and devices and is slated to be crowned the king in foreseeable future.

The Transistor Structure

The Fermi-FET is a unique patented variation of the broad class of devices known as “Field Effect Transistors” (FET). Although the transistor operation differs markedly from standard MOSFET devices, the structure of the new device has many similarities, thus permitting easy conversion of existing CMOS process lines to production of Fermi-FET transistors.

Basic FET

The basic principle behind the working of a Field Effect Transistor is the conducting semi-conductor channel between two ohmic contacts; source and drain. The gate terminal controls the channel current and is a very high-impedance terminal. The FET is thus a three terminal, unipolar device. The name ‘field effect’ is due to the fact that the current flow is controlled by potential set up in the device by an external applied voltage. There are two types of FETs – JFET and MOSFET. The FET of interest here is the MOSFET.

The N-channel MOSFET has two lightly heavily doped n- regions diffused into a lightly doped p-type substrate; separated by 25 μm.These n-regions act as source and drain. An insulating layer is grown over the surface. Metal contacts are made for the source and drain. A conducting layer of metal will act as the gate, overlaying the insulating layer over the entire channel region. Due to the presence of the insulating layer, the device is called Insulated Gate FET (IGFET) or Metal Oxide Semiconductor FET ( MOSFET).

Modern Complementary MOS (CMOS) processes incorporate polysilicon gate structures less than 0.25 micron long, with the most common process being 0.15µm. At this geometry, and the standard 1.8 volt Vdd, oxide spacers and drain extensions are common. Most processes also make use of the oxide spacer to form salicide on the gate and diffusions to reduce the sheet resistance and to control the polytime constant on wide transistors.

Surface Channel Inversion Devices

Most short channel CMOS processes create SCI type transistors for both P and N-Channel devices. This decision has evolved as line widths attained shorter dimensions primarily due to the reduced short channel effect sensitivity of the SCI devices over the BCA transistor,traditionally used for the PMOS. Its because of the widely known control problems with deep buried channel transistor (BCA) technology that most short channel processes incorporate both n-type and p-type polysilicon gates to create surface channel inversion (SCI) devices for both transistor polarities.

SCI STRUCTURE

Figure 1 – A cross-section drawing of an N-Channel SCI MOSFET transistor. The polysilicon gate would be degeneratively doped n-type. The drain extension region is typically utilized to reduce short channel effects (SCE).

Figure 1 depicts the main features of a short channel NMOS SCI device. Certain other refinements aimed at reducing short channel effects such as pocket implants, SSR well, graded channel, and elevated diffusions have been ignored for simplicity.

SCI OPERATION

The operation of surface channel transistors is relatively simple to envision. Figure 2 shows an enlargement of the channel region with the source end drain extension from Figure 1. As the gate electrode is biased from zero (fully off) toward the threshold voltage, the initial charge on the gate drives free holes in the substrate away from the gate region.

Figure 2 – A close-up of the channel region in Fig. 1 near the drain side of the gate. The gate electrode has a positive bias but is below threshold voltage. The silicon depleted of mobile carriers is shown as a white area. The arrows represent the vertical field direction.

The combination of depletion charge on the gate and induced space charged depletion region in the substrate create a vertical electric field through the dielectric and into the substrate. This impedes carrier movement and hence decreases carrier mobility. This is a major disadvantage of SCI transistors affecting device performance to a large extent.

Device scaling has forced the gate oxide to become ever thinner and the average doping in the well region to increase. These lead to reductions in carrier mobility; the ease with which charges can move through the transistor producing drive current.

Figure 3 – The same region as in Fig. 2, but the gate bias is now just above the threshold. The depletion region has reached its maximum depth and a thin region of “inverted” silicon (n-type carriers in p-type silicon) exists just below the gate oxide. The arrows represent the vertical field and consist of two parts. The first part supports the depletion region and the second part reflects the carriers in the inversion layer.

As the gate bias continues more positive, the threshold voltage is reached. At this point the depleted silicon region under the gate stops expanding and additional charge on the gate results in free conduction carriers from the diffusion moving to the region under the gate (see Figure 3). It is these carriers that are responsible for the output current of the transistor.

PROBLEMS WITH SCI

It should be noted that for an SCI device, good short channel performance requires high channel doping to counteract short channel induced leakage and threshold drop, but at the same time needs a low threshold voltage due to the low operating voltages of short channel processes. This dictates the thinnest possible gate oxide must be used.

The thin gate oxide and high vertical electric fields have caused a new challenge not previously large enough to cause difficulties; polysilicon depletion. Polysilicon depletion occurs when free carriers are swept away from the bottom of the poly gate due to high vertical fields. In an SCI type of device, this occurs when the transistor is fully turned on. As can be seen in Figure 3, this depletion causes the gate dielectric to appear thicker than it actually is, reducing transistor performance.

In summary, SCI devices, the current device used in many short channel applications, have three major design difficulties:

• High Capacitance – As SCI devices shrink, the higher substrate doping causes increased parasitic junction capacitance around the source and drain regions.

• Lowered Channel Mobility – Higher channel doping and increased vertical electric field make it more difficult for carriers to move across the channel.

• Polysilicon Depletion – The high charge on the gate can cause polysilicon depletion to occur, lowering the transistor drive current.

Buried Channel Accumulation Devices

At longer channel widths, the BCA architecture was widely used for the P-Channel transistor in CMOS processes. This was primarily done because the BCA transistor would use the same n-type polysilicon gate used by the N-Channel device, greatly simplifying the process. Recently it became apparent to most manufacturers that the BCA architecture was incapable of scaling to the very fine line widths in development today. The added process complexity of using both n-type and p-type poly was offset by the better SCE immunity of the SCI transistor.

BCA STRUCTURE

Figure 4 – A cross-section drawing of an N-Channel BCA transistor. Note that the polysilicon gate would be doped p-type. The drain and source extensions are connected by an n-type channel layer.An N-Channel BCA device would be built with the structure shown in figure 4. The polysilicon electrode is p+, and there is an n-type channel between the source and drain. The depth of the channel is minimized to reduce short channel effects (SCE).

BCA OPERATION

Although the structure of a BCA device is very similar to a SCI transistor, the operation of the two is markedly different. This is due to the presence of the p-n junction formed by the “channel” and well regions abutting. As in all p-n junctions, free carriers diffuse across the junction until the retarding field, due to the ionized donor and acceptor atoms, causes the drift and diffusion flows to equalize. This field leads to the built-in potential of p-n junctions. The magnitude of this built-in potential is determined by the doping density of the silicon on both sides of the junction.

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This potential causes carrier depletion on either side of the metallurgical junction. The widths of these depletion regions are proportional to the relative doping of the p and n regions. In traditional BCA architectures, the “channel” region is more highly doped than the well region beneath it. The arrows in Figure 6 show the vertical electric fields present with the gate electrode at zero bias.

Figure 5 – A close-up of the channel region from Fig. 4 above.

The dashed line depicts the location of the p-n junction and depleted silicon is shown as a white area. The arrows represent the vertical field direction.Note that the junction potential is not high enough to fully deplete the entire channel region. There is another field due to the gate work function that also depletes the surface part of the channel region.

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This potential also causes some depletion of charge near the bottom surface of the gate. Since the gate doping is usually very high the depletion width in the gate is small, but as channel lengths shrink, this can become an important effect in the subthreshold region.

Figure 6 – A graph depicting the vertical electric field on a line normal to the silicon surface under the conditions of Figure 5. Wjn and W jp make up the space-charge region due to the metallurgical junction. The region labeled Wpn is depleted due to the potential difference between the gate and the channel. This charge is reflected in the poly depletion Wpp .

Figure 6 shows the vertical electric field in the wafer with the gate electrode at zero bias (as in Fig. 5). Note that the field reverses direction within the channel region where the depletion from the junction Wjnmeets the depletion induced from the gate electrode Wpn.

As the gate electrode bias is moved from zero towards Vdd , the field from the gate initially decreases reaching zero at Vt . The gate field then reverses and begins to climb as more charge is injected into the channel at the source electrode. Figure 7 shows the conduction channel forming just above the junction depletion region.

Figure 7 – The channel region from Fig. 5 above, with the gate bias at just above the threshold voltage. The channel begins to open near the edge of the junction depletion region and widens toward the surface as neutral silicon until the surface is reached. High-level injection begins after this point.

ADVANTAGES OF BCA

BCA devices have a significant advantage over SCI devices in terms of channel mobility. This is due to two reasons.

• First, the vertical field within the channel is substantially lower in a BCA device. This is because the gate does not have to deplete majority carriers away from the interface to form a channel. The gate supplied vertical field is due only to the mobile conduction charge.

• Second, improvement in channel mobility because this architecture can be made with a significantly lower total doping density in the channel. This improved channel mobility is a major advantage over traditional surface channel inversion devices.

Figure 8 – The vertical electric field on a line normal to the silicon surface under the conditions of Figure 7. Note the neutral region above Wjn below Wpn . Increasing the gate bias will reduce Wpn and Wpp but leave the junction field largely unchanged.

Figure 8 shows the vertical electric field associated with a transistor in the condition shown in Figure 7. Further increases in gate bias result in the channel width increasing toward the surface and then excess carriers are injected with an exponential distribution peaked slightly beneath the interface, as shown in Figure 9.

Figure 9 – With sufficient gate bias, the channel is under high-level injection. Since the carriers are majority type the only vertical field present within the conducting layer is that due to the conduction carriers themselves.

Note that the junction depletion region remains largely unchanged during the gate sweep. Figure 9 shows the vertical field profile with the gate bias near Vdd. Even though the conduction carrier distribution at this point has the same exponential shape as an SCI device, the distribution width is greater in the BCA and the peak concentration is lower. This decreases carrier-carrier interactions also helping BCA channel mobility.