EMF4086 RF Transistor Circuit Design RT1
FACULTY OF ENGINEERING
LAB SHEET
EMF4086 RF TRANSISTOR CIRCUIT DESIGN
TRIMESTER 2 (2014/2015)
RT1 – RF Amplifier Design
*Note: On-the-spot evaluation may be carried out during or at the end of the experiment. Students are advised to read through this lab sheet before doing experiment. Your performance, teamwork effort, and learning attitude will count towards the marks.
RT1 – Designing A Constant Power Gain Amplifier
Introduction
In this experiment you are going to design a simple single-stage bipolar junction transistor (BJT) amplifier with a power gain of +20dB into 50W load and operating at 600MHz. The design is carried out using the software Advance Design System by Agilent Technologies. Follow the procedures outlined below.
Overview of Design Procedures
A typical design flow for small signal amplifier is shown in Figure 1:
Figure 1 – Amplifier block diagram and small-signal amplifier design cycle.
We are going to design a small-signal amplifier with a specific gain at 600MHz, the other parameters such as input and output VSWR (voltage standing wave ratio) and noise figure are not considered. Therefore only the steps underlined in Figure 1 are implemented.
The Detailed Design Procedures
Step 1 – Run ADS software
Log into Windows workstation (username and password would be supplied to you). Run Advance Design System software from the start menu as shown in Figure 2 or from the icon on the desktop.
or
Figure 2 – Running ADS.
Step 2 – Create a new project
From the main window of ADS, create a new project named “EMG4086” under the folder “D:\ADS\default\”.
Figure 3 – Creating a new project “EMG4086”.
A new Schematic window will automatically appears once the project is properly created. Otherwise you can manually open a new Schematic window by double clicking the Create New Schematic button on the main window. The work area is shown in Figure 4 below.
Figure 4 – The schematic work area.
Step 3 – Drawing the basic circuit
The first step is to choose a suitable transistor for the job. For this example we select the NPN wide-band transistor BFR92A. This transistor comes in an SOT-23 package and has a transition frequency fT of 5.0GHz. Both Infineon Technologies and NXP Semiconductor (formerly Phillips Semiconductors) manufacture this device. You can get a model of this transistor from the component library . Use the search function to look for “bfr92a” as illustrated in Figure 5A. There are many versions of the model, you should use the one with the description “BRF92A: SOT23 Package….”. This model simulates the transistor based on the laws of the device physic, taking into account the package parasitic capacitance and inductance. The other models are ‘black box’ models based on S-parameters measurement. These are only accurate for a certain d.c. bias condition. Datasheet for this transistor can also be obtained from the manufacturers websites. The actual transistor is shown in Figure 5B.
Figure 5A – Getting the transistor BFR92A from the component library.
Figure 5B – Top view of BFR92A transistor from NXP Semiconductor.
Use the following component pallette to access the components button:
· Lumped Component Palette – inductor, resistor and capacitor .
· Sources -Time Domain Palette – d.c. voltage source .
· Simulation-DC – DC simulation control .
Construct the circuit as shown in Figure 6. This is a common-emitter configuration with RF chokes Lb1 and Lb2 to isolate the d.c. biasing components from the transistor.
Figure 6 – The basic amplifier circuit for d.c. simulation.
Step 4 – Perform d.c. Simulation to Ensure Transistor is Operating in Active Region
Run the d.c. simulation by clicking the simulation button on the Schematic window . You can view the d.c. voltage and current on every nodes and wires on the circuit by activating the d.c. annotation command as shown in Figure 7 below. Go to the Simulate menu and select annotate dc solution. The important voltages and current are shown in Table 1. Observe that BE junction of Q1 is forward biased while BC junction or Q1 is reversed biased, thus the transistor is operating in active region. The collector current IC and VCE affects the value of the small-signal S-parameters to be obtained later.
Figure 7 – To display the d.c. solution results on the schematic window.
VB / VC / VE / IC1.39V / 5.0V / 0.60V / 5.9mA
Table 1 – The d.c. solution.
Step 5 – Modify the Schematic S-Parameter Simulation
After performing the d.c. simulation, modify the schematic of Figure 6 for S-parameters simulation. Include the coupling capacitors Cc1 and Cc2. Accessing the Simulation-S_Param component palette, insert the control and termination for S-parameters simulation. Set the parameters for simulation and termination as shown in Figure 8. Note the numbering of the termination, 1 for input port and 2 for output port. We are going to run frequency sweep from 50MHz to 1.0GHz at a step of 1.0MHz.
The software actually run a linear small-signal frequency domain simulation and calculates the S-parameter using
where Vi and Ii are the voltage and current on the ith node.
Figure 8 – Schematic for performing S-parameter simulation.
Before you run the simulation for Figure 8, save the schematic as “bjt_amplifier.dsn” as illustrated in Figure 9.
Figure 9 – Saving the schematic or network (as it is known in ADS).
Step 6 – Perform S-Parameter Simulation
Run the simulation of the schematic in Figure 8. A Data Display window will automatically pop up, if it does not you can manually call up a Data Display window using the button on the Schematic window. You can now display the S-Parameters S11, S22, S12 and S21 as a function of frequency as shown in Figure 10.
Figure 10 – Selecting a trace to be shown in a plot.
The complete S-parameters are shown in Figure 11 and Figure 12. Since the S-parameters are complex quantities, S12 and S21 are shown as X-Y plot of the magnitude and phase versus frequency. S11 and S22 are displayed in Smith Chart format. Use the button to insert X-Y plot and the button to insert a Smith Chart.
Hint: By using a Marker, you can read the value from the graph. Double-clicking on each line allows you to change the property of the lines such as thickness and colour.
Figure 11 – X-Y Plot of S12 and S21 versus frequency.
Figure 12 – Smith Chart display of S11 and S22 versus frequency.
Step 7 – Stability Check
After obtaining the S-parameters, we could check the stability of the amplifier circuit at various frequencies. This can be carried out by plotting the Roulette stability factor (K) and D which are function of S-parameters:
When K > 1 and |D| < 1, the amplifier is unconditionally stable, otherwise it is conditionally stable or totally unstable.
We can plot K and |D| by defining equations in the Data Display window. Insert an equation using the button . The definition for K and |D| are shown in Figure 13. These are then plotted as X-Y plot and is depicted in Figure 15. Note that ADS also has built-in function to define the parameter K, which is the function stab_fact( ).
Figure 13 – Definition for Roulette Stability Factor K and |D|.
To insert data from equation, use the button to insert an X-Y plot and select “Equations” from the “Datasets and Equations” drop-down menu. Make sure the dataset is “bjt_amplifier”, which is the name of the schematic.
Figure 14 – Selecting the equation data instead of simulation data to plot K and |D|.
Figure 15 – K and |D| versus frequency.
Using a marker, it is seen from Figure 15 that K<1 and |D|<1 at f = 600MHz. Therefore the amplifier is conditionally stable. The means there are certain source and load impedance which might cause the amplifier to become unstable and oscillate. To determine the region of instability, we must plot the Source Stability Circle and Load Stability Circle in the next step.
Step 7 – Plotting Stability Circles
Before we proceed, save the schematic as a new file name “bjt_amplifier_600Mhz.dsn”. The preceding simulation for “bjt_amplifier.dsn” runs the S-Parameters simulation for a range of frequency. Now we would like to specifically concentrate on the frequency 600MHz, our frequency of interest. Hence the name “bjt_amplifier_600MHz.dsn”. Modify the S-Parameter simulation control as shown in Figure 16 for single point simulation.
Figure 16 – Single point simulation at 600MHz.
Simulate the new schematic and a new Data Display window will appear (or you can manually call up a new one). Now define two equations as in Figure 17. These equations uses built-in functions s_stab_circle( ) and l_stab_circle( ). These functions actually implement the stability circle equations for source reflection coefficient Gs and load reflection coefficient GL as follows:
Figure 17 – Definition for source and load stability circles.
The s_stab_circle( S,51) function plots the Source Stability Circle for Gs using current S-parameters value and forming the circle using 51 data points. Similarly for l_stab_circle(S,51) plots the Load Stability Circle for GL using 51 data points. Use the table button to display the values of S11 and S22 and 600MHz as shown in Figure 18.
Figure 18 – S11 and S22 at 600MHz.
The stability circles are plotted on the extended Smith Chart in Figure 19. From Figure 17, |S11| and |S22| are less than unity at 600MHz, hence the stable region is outside the circles from stability theory (see lecture notes). Thus if we were to design an amplifier, the source reflection coefficient and the load reflection coefficient as seen by the amplifier must reside in the stable region. The next step is to plot the locus of constant power gain, and to make sure that at least some part of the locus falls in the stable region.
Figure 19 – The Source and Load Stability Circles. The shaded region is the stable region for both source and load reflection coefficient.
Step 8 – Plotting the Constant Power Gain Circles and Finding the Optimum Load Impedance
Using the Data Display window for “bjt_amplifier_600Mhz.dsn”, we add the following definition for constant power gain circles depicted in Figure 20.
Figure 20 – Definition for constant power gain circles, for 10dB, 15dB and 20dB.
Again this is a built-in function in ADS, which plot all the GL points on the Smith Chart, which fulfills . Here x is 10, 15 and 20.
For instance, the definition gp_circle(S,15,51) in Figure 19 means Gp(GL) = 15dB circle using 51 data points and current S-Parameters. The constant power gain circles are plotted together with the Source and Load Stability Circles in Figure 21.
Step 9 – Time Domain Simulation and Verfication
Figure 21 – Constant power gain circles.
An important observation in Figure 21 is that as we increase the power gain of the amplifier, the required load reflection coefficient GL will move towards the margin of stability. This is reasonable because as we increase the gain of an amplifier, the tendency to oscillate increases as any small amount of feedback will result in uncontrolled positive feedback and hence oscillation. The amount of feedback in the amplifier is given by the S12. Since we want an amplifier with +20dB gain at 600MHz, the load reflection coefficient must falls on the Gp = 20dB circle. We choose the value marked by the marker in Figure 21. This value is the furthest away from the Load Stability Circle; hence it will be less affected by changes in the stability circle due to parameters variation of the transistor.
From the marker position, the value of optimum load is approximately (Zo is the impedance value of components TERM1 and TERM2 in the schematic):
At 600MHz, this load can be modeled by a 90.1Ohm resistor in series with 38.8nH inductor. If the actual load that is connected to the amplifier is not this network, we could employ an impedance transformation network to transform the actual load network to produce this equivalent value at 600MHz.
Figure 22 – Equivalent load at 600MHz for amplifier.
Step 9 – Time Domain Verification
Now we want to perform a time domain simulation to verify our circuit. Save the current schematic as “bjt_amplifier_600MHz_td.dsn” and modify the schematic to the one shown in Figure 23. You will need to change the component palette to Sources-Time Domain and Simulation-Transient to access the Sine Voltage Source and the Transient Simulation Control buttons. You will also need to name the input and output node as Vin and Vout as in Figure 23. Access the Name Wire/Node button on the Schematic window. A dialog box as shown in Figure 23 will appear, type the name of the input node and click on the node to be named Vin in the schematic. Repeat the similar procedures for Vout.
Figure 23 – Name the input node as Vin and the output node as Vout.
Figure 24 – The final schematic for time domain simulation.
Finally run the simulation of the schematic in Figure 24. Plot the time domain waveform for Vin and Vout on a new Data Display window. The result is shown in Figure 25.