CSE 171 Lab 6. October 18-20, 2004.Rev. A

EXPERIMENT: Adder/Subtractor

PRE-LAB

  1. Study Sec. 7.1 Adders, pages 110-117 and Sec. 7.2 Subtractors, pages 117-121. The objective of this lab is to design a module that implements a 4-bit adder/subtractor in a Xilinx XC95108 CPLD on a PLDT-3 trainer board that adds or subtracts two 4-bit binary operands and displays the result on the 7-segment display as either a signed or an unsigned decimal number.
  2. A module DisplSel is used to convert the 4-bit output from an adder/subtractor to the desired form for display, unsigned or signed (see Figure 1).

The inputs are a 4-bit binary number B3..B0 and a select input value s that selects the desired display mode, s = 0 for unsigned numbers, s = 1 for signed numbers. This module uses the Bin4BCD module from Lab 5 to process unsigned numbers and the absval module from Lab 4 to process signed numbers. The output U3..U0 is the 4-bit value of the units digit for both unsigned and signed numbers. For unsigned numbers, the output signal Ten is the value of the tens digit, 0 or 1. For signed numbers, the output signal Minus is a one for negative numbers, zero for positive numbers.

  1. Using Figure 1 as a guide, write an ABEL program DisplaySelect.abl for a module DisplSel as a functional block. Include an interface statement for this module and declarations for the two included modules, Bin4BCD and absval. Declare the input and output signals but do not assign pin numbers. Include definitions Bin = [B3..B0], Units = [U3..U0]. Write equations for the inputs to the two functional blocks and for the indicated output signals. Complete the following test vectors to test all possible states of the 4-bit binary input, first for s=0, then for s=1:

@radix 16;

TEST_VECTORS([s,Bin] -> [Minus,Ten,Units])

[0, 0] -> [0,0, 0];

[0, 1] -> [0,0, 1];

[0, 2] -> [0,0, 2];

: : :

Print out copies of your DisplaySelect.abl, BinToBCD.abl, and AbsValue.abl file listings.

  1. Write an ABEL program called Lab6.abl as a top-level module AddDispl that combines the addsub module written for Group Homework #4, the above DisplSel module, and the hex7seg module developed for Lab 3 (see Figure 2).

Using Figure 2 as a guide, declare the functional blocks shown, input signals A = [A3..A0] for the four toggle switches on S6, B = [B3..B0] for the four toggle switches on S7, E assigned to pushbutton S1, s assigned to pushbutton S2, and the indicated output signals. Write equations to connect the modules as shown. Do not include test vectors for this module. Print out copies of your completed Lab6.abl file, your AddSubtract.abl file from Group Homework #4, and your hex7seg.abl file from Lab 5.

LAB

  1. Create a new project AddSub in a folder called <your name> under C:\CSE171 using the Xilinx Project Navigator program and add a copy of your AddSubtract.abl file. Simulate your ABLE program and print out the BLIF Simulation Report and the AddSubtract.abl file listing.
  2. Create a new project, Lab6 in a folder called <your name> under C:\CSE171 and add copies of your DisplaySelect.abl, BinToBCD.abl, and AbsValue.abl files. Simulate your DisplaySelect.abl program and print out the BLIF Simulation Report. Print out copies of your DisplaySelect.abl, BinToBCD.abl, and AbsValue.abl file listings.
  3. Add copies of your Lab6.ablfile, your AddSubtract.abl file, and a copy of your 7segment display decoder, hex7seg.abl. Generate a programming file and print out copies of the Lab6.abl and hex7seg.abl file listings.
  4. Prepare the PLDT-3 board by using jumper wires to connect connectors T2 and T4 to pins 72 and 71 respectively of header HD2. Connect the PC printer port cable to the PLDT-3 board, and then connect the 9V DC power module. Download your program to the Xilinx chip. The PLDT-3 board should now function as an adder/subtractor with unsigned and signed decimal display of the results.
  5. The four toggle switches of S6 represent A3..A0, those of S7 represent B3..B0. Set the toggle switches to each set of the test values shown in the following table and observe the OVF and CBF flags displayed in LEDs 9 and 12 respectively and the SD3..SD0 values displayed in LEDs 13 to 16, both for addition (S1 released) and for subtraction (S1 pressed). For each addition and subtraction operation, observe the results on the 7-segment display, both for the unsigned (S2 released) and signed (S2 pressed) results. Record your observations in Table 2 below.

Test Values (Binary) / S1
Setting / LED Display (Binary) / 7-seg. Display (Decimal)
A3..A0 / B3..B0 / SD3..SD0 / OVF / CBF / Unsigned / Signed
0101 / 0010 / Add
Subtract
0100 / 0111 / Add
Subtract
1100 / 0111 / Add
Subtract
1011 / 1100 / Add
Subtract

Table 2 – Experimental Observations

  1. Collect the following together with your name(s) on the front, demonstrate your design to your lab instructor and obtain his/her signature for your work.:
  2. The Lab6.abl listing.
  3. The AddSubtract.abl listing.
  4. The BLIF Simulation Report listing for the AddSubtract.abl file.
  5. The DisplaySelect.abl listing.
  6. The BLIF Simulation Report listing for the DisplaySelect.abl file.
  7. The BinToBCD.abl listing.
  8. The AbsValue.abl listing.
  9. The hex7seg.abl listing.
  10. For each of the eight cases in Table 2, explain the operands and result twice, first as unsigned numbers, then as signed numbers. Use these results to explain the values obtained for the OVF and CBF flags.
  11. Erase your program and remove power from the Xilinx CPLD, delete the directory C:\CSE171\<your name> that you created at the beginning of this lab, remove any other files or folders you put on the system and empty the Recycle Bin.

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